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| Number | Title | Issue Date |
| 7427776 | Thin-film transistor and methods A thin-film transistor (TFT) is fabricated by providing a substrate, depositing and patterning a metal gate, anodizing the patterned metal gate to form a gate dielectric on the metal gate, depositing and patterning a channel layer comprising a multi-cation oxide ove... | 09/23/2008 |
| 7414298 | Super self-aligned collector device for mono-and hetero bipolar junction transistors, and method of making same The invention relates to a process of forming a compact bipolar junction transistor (BJT) that includes forming a self-aligned collector tap adjacent the emitter stack and an isolation structure. A base layer is formed from epitaxial silicon that is disposed in the ... | 08/19/2008 |
| 7354820 | Heterojunction bipolar transistor with dielectric assisted planarized contacts and method for fabricating A method for fabricating an HBT is disclosed, wherein successive emitter, base, collector and sub-collector epitaxial layers are deposited on a substrate, with the substrate being adjacent to the sub-collector layer. The epitaxial layers are etched to provide locati... | 04/08/2008 |
| 7303968 | Semiconductor device and method having multiple subcollectors formed on a common wafer A semiconductor device and a method of fabricating a semiconductor device having multiple subcollectors which are formed in a common wafer, in order to provide multiple structures having different characteristic and frequency response are provided. The subcollectors... | 12/04/2007 |
| 7297589 | Transistor device and method A method for making a heterojunction bipolar transistor includes the following steps: forming a heterojunction bipolar transistor by depositing, on a substrate, subcollector, collector, base, and emitter regions of semiconductor material; the step of depositing the ... | 11/20/2007 |
| 7285457 | Heterojunction bipolar transistor and manufacturing method thereof In the method for manufacturing a heterojunction bipolar transistor, a collector contact layer, a collector layer, a base layer, a base protection layer, an emitter layer, an emitter contact layer, and a WSi layer are sequentially formed on a substrate. A resist pat... | 10/23/2007 |
| 7264987 | Method of fabricating optoelectronic integrated circuit chip Provided is a method of fabricating an optoelectronic integrated circuit chip. In particular, a method of fabricating an optoelectronic integrated circuit chip is provided, in which an optical absorption layer of a wave-guide type optical detector is grown to be thi... | 09/04/2007 |
| 7256433 | Bipolar transistor and a method of manufacturing the same A bipolar transistor having enhanced characteristics is fabricated by etching a base mesa, which is formed below an emitter mesa (upper emitter layer) and a base electrode, so as to have jut regions on the edges of its generally rectangular region. A mask film, e.g.... | 08/14/2007 |
| 7145174 | Semiconductor device A semiconductor device can include a channel including a zinc-indium oxide film. ... | 12/05/2006 |
| 6683332 | Heterojunction bipolar transistor and manufacturing method therefor including electrode alloyed reaction layers A Pt alloyed reaction layer is formed under a base ohmic electrode. This alloyed reaction layer extends through a base protective layer so as to reach a base layer. Besides, a Pt alloyed reaction layer is formed under an emitter ohmic electrode. This allo... | 01/27/2004 |
| 6680497 | Interstitial diffusion barrier A heterojunction bipolar transistor is doped in the sub-collector layer (20) with phosphorus (24). The presence of the phosphorus causes any interstitial gallium (22) to be bonded (26) to the phosphorus (24) and move to a lattice site. The result is that ... | 01/20/2004 |
| 6680236 | Ion-implantation and shallow etching to produce effective edge termination in high-voltage heterojunction bipolar transistors A method is provided for improving edge terminations in a semiconductor device while maintaining breakdown voltage of said semiconductor device at or near its theoretical limit. The method comprises: employing ion-implantation to create a compensated regi... | 01/20/2004 |
| 6680494 | Ultra high speed heterojunction bipolar transistor having a cantilevered base Reduction in the base to collector capacitance of a heterojunction bipolar transistor, and, improved high frequency performance is achieved using existing materials and processes by undercutting the collector (5) under the base (7) along two parallel side... | 01/20/2004 |
| 6677625 | Bipolar transistor The invention provides a bipolar transistor attaining large MSG and a method of fabricating the same. The bipolar transistor of this invention includes a collector layer; abase layer deposited on the collector layer; and a semiconductor layer deposited on... | 01/13/2004 |
| 6673687 | Method for fabrication of a heterojunction bipolar transistor According to one disclosed embodiment, a heavily doped subcollector is formed. Subsequently, a collector is fabricated over the heavily-doped subcollectoi, wherein the collector comprises a medium-doped collector layer adjacent to the subcollector and a l... | 01/06/2004 |
| 6670653 | InP collector InGaAsSb base DHBT device and method of forming same A Double Heterojunction Bipolar Transistor (DHBT) is disclosed employing a collector of InP, an emitter of InP or other material such as InAlAs, and a base of either a selected Inx Ga1-x Asy Sb1-y compound, whic... | 12/30/2003 |
| 6667498 | Nitride semiconductor stack and its semiconductor device A transistor structure is implemented which can achieve high current gain by causing electrons injected from an emitter to reach a collector. An InGaN graded layer, which is interposed between a p-type InGaN layer and an n-type GaN layer, includes an In c... | 12/23/2003 |
| 6664610 | Bipolar transistor and the method of manufacturing the same This invention provides a new configuration and manufacturing method of the hetero-junction bipolar transistor. According to the invention, the HBT comprises a semi-insulating InP substrate, a buffer layer on the substrate, a sub-collector layer, a collec... | 12/16/2003 |
| 6661037 | Low emitter resistance contacts to GaAs high speed HBT A heterojunction bipolar transistor is provided having an improved current gain cutoff frequency. The heterojunction bipolar transistor includes a contact region formed from InGaAsSb. The contact region allows an emitter region of the heterojunction bipol... | 12/09/2003 |
| 6661038 | Semiconductor device and method of producing the same A semiconductor device of the present invention includes a systematic structure layer of first conductivity type and having a systematically arranged structure. The systematic structure layer is formed on a collector contact layer of first conductivity ty... | 12/09/2003 |
| 6649458 | Method for manufacturing semiconductor device with hetero junction bipolar transistor The present invention achieves the enhancement of a manufacturing yield factor and the reduction of manufacturing cost in a manufacturing method of a semiconductor device having a hetero junction bipolar transistor (HBT), a Schottky diode and a resistance... | 11/18/2003 |
| 6646293 | Structure for fabricating high electron mobility transistors utilizing the formation of complaint substrates High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a la... | 11/11/2003 |
| 6639300 | Semiconductor integrated circuit having an integrated resistance region A semiconductor integrated circuit device comprises an active device and a resistance element formed monolithically on a common substrate wherein the resistance element includes a dummy pattern having a layered structure identical with a layered structure... | 10/28/2003 |
| 6605519 | Method for thin film lift-off processes using lateral extended etching masks and device A method for forming an etching mask structure on a substrate includes etching the substrate, laterally expanding the etching mask structure, and depositing a self-aligned metal layer that is aligned to the originally masked area. The etching can be isotr... | 08/12/2003 |
| 6593604 | Heterojunction bipolar transistor, manufacturing method therefor, and communication device therewith An emitter of a heterojunction bipolar transistor has a double-layer protrusion formed of a first emitter layer and a second emitter layer and protruded outside an external base region. The protrusion of 50 nm in total thickness is enough to prevent damag... | 07/15/2003 |
| 6583468 | Semiconductor element An AlN film as an underlayer is epitaxially grown on a substrate having a dislocation density of 1011 /cm2 or below and a crystallinity of 90 seconds or below in full width at half maximum (FWHM) of an X-ray rocking curve at (002) re... | 06/24/2003 |
| 6580139 | Monolithically integrated sensing device and method of manufacture A monolithically integrated, compound semiconductor sensing device and a method of making the device is provided. The device includes an signal conditioning circuit formed on a substrate surface. A sensor including one or more compound semiconductors is d... | 06/17/2003 |
| 6579741 | Monolithically integrated sensing device and method of manufacture A method of manufacturing a monolithic compound semiconductor sensing device includes epitaxially depositing a signal conditioning epitaxy on a substrate surface, providing a well in the signal conditioning circuit and exposing the substrate surface, and ... | 06/17/2003 |
| 6566693 | Reduced capacitance scaled HBT using a separate base post layer High-speed, low capacitance heterojunction bipolar transistors (HBTs) and a method for their fabrication are disclosed. The devices are fabricated by a manufacturable process which moves patterning and deposition of the base post up versus the current man... | 05/20/2003 |
| 6563145 | Methods and apparatus for a composite collector double heterojunction bipolar transistor A compound collector double heterojunction bipolar transistor (CCHBT) incorporates a collector comprising two layers: a wide bandgap collector region (e.g., GaAs), and a narrow bandgap collector region (e.g., InGaP). The higher electric field is supported... | 05/13/2003 |
| 6559482 | III-N compound semiconductor bipolar transistor structure and method of manufacture A III-N compound semiconductor bipolar transistor structure and method of manufacture. An epitaxial layer structure is formed over a substrate. The epitaxial layer structure includes a nucleation layer, a buffer layer, an emitter layer containing first ty... | 05/06/2003 |
| 6541346 | Method and apparatus for a self-aligned heterojunction bipolar transistor using dielectric assisted metal liftoff process Disclosed is a manufacturing method to fabricate Heterojunction Bipolar Transistors (HBTs) that enables self-alignment of emitter and base metal contact layers with precise sub-micron spacing using a dielectric-assisted metal lift-off process. Such an HBT... | 04/01/2003 |
| 6531722 | Bipolar transistor The present invention relates to a hetero-bipolar transistor. This transistor comprises a semi-insulating InP substrate, a buffer layer on the substrate, a sub-collector layer on the buffer layer, a collector layer on the sub-collector layer, a base layer... | 03/11/2003 |
| 6531721 | Structure for a heterojunction bipolar transistor According to one disclosed embodiment, a heavily doped subcollector is formed. Subsequently, a collector is fabricated over the heavily-doped subcollector, wherein the collector comprises a medium-doped collector layer adjacent to the subcollector and a l... | 03/11/2003 |
| 6528378 | Semiconductor device To provide a super high-speed heterojunction bipolar transistor, a semiconductor device including such a heterojunction bipolar transistor has a structure wherein a subcollector layer, collector layer, base layer, emitter layer (InGaP layer) and emitter c... | 03/04/2003 |
| 6525349 | Heterojunction bipolar transistor with tensile graded carbon-doped base layer grown by MOCVD A heterojunction bipolar transistor (HBT), having a substrate formed of indium phosphide (InP), and having emitter, base and collector layers formed over the substrate such that the base layer is disposed between the emitter and collector layers. The coll... | 02/25/2003 |
| 6495869 | Method of manufacturing a double-heterojunction bipolar transistor on III-V material The invention relates to a method of manufacturing a double heterojunction bipolar transistor (1) comprising successively at least one sub-collector layer, a collector layer, a base layer and a metallic layer (10) deposited on the said base layer; the sai... | 12/17/2002 |
| 6482712 | Method for fabricating a bipolar semiconductor device A method for fabricating a bipolar device, including the steps of forming an epitaxial growth retarding layer on a substrate at a predetermined angle, forming a collector layer on the substrate so that the collector layer is adjacent the epitaxial growth ... | 11/19/2002 |
| 6482711 | InPSb/InAs BJT device and method of making Bipolar junction transistor (BJT) devices, particularly heterojunction bipolar transistor (HBT) devices, and methods of making same are described. A combination of InPSb and p-type InAs is used to create extremely high speed bipolar devices which, due to ... | 11/19/2002 |
| 6465816 | Semiconductor device and manufacturing method of the same A semiconductor device is a hetero-junction bipolar transistor structured by having a gallium arsenide film among laminated films, which has an indium gallium phosphide (InGaP) film which is connected to the gallium arsenide film and functions as an emitt... | 10/15/2002 |
