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| Number | Title | Issue Date |
| 6646304 | Universal semiconductor wafer for high-voltage semiconductor components A universal semiconductor wafer for high-voltage semiconductor components includes at least one layer of a first conductivity type which is provided on a semiconductor substrate of the first conductivity type. A plurality of floating semiconductor zones o... | 11/11/2003 |
| 6630711 | Semiconductor structures with trench contacts Semiconductor structures such as the trench and planar MOSFETs (UMOS), trench and planar IGBTs and trench MCTs using trenches to establish a conductor. Improved control of the parasitic transistor in the trench MOSFET is also achieved and cell size and pi... | 10/07/2003 |
| 6509607 | Semiconductor device with reduced source diffusion distance and method of making same A semiconductor device comprising a drain region, a body region overlying the drain region and defining an upper surface, source regions extending from adjacent the upper surface of the body region towards the drain region, and a series of indentations ex... | 01/21/2003 |
| 6501128 | Insulated gate transistor and the method of manufacturing the same An IGBT that exhibits a low on-voltage and a sufficient short circuit withstand capability and to provide a method of manufacturing such an IGBT. The p-type well region and the n-type emitter region are not formed by the self-alignment technique using the... | 12/31/2002 |
| 6437399 | Semiconductor structures with trench contacts Semiconductor structures such as the trench and planar MOSFETs (UMOS), trench and planar IGBTs and trench MCTs using trenches to establish a conductor. Improved control of the parasitic transistor in the trench MOSFET is also achieved and cell size and pi... | 08/20/2002 |
| 6225643 | SOI cell and method for producing it An SOI cell includes a semiconductor body having at least one insulator layer. A polycrystalline zone doped with a dopant of a first conductivity type is grown on the insulator layer. The polycrystalline zone is adjoined outside the region of the insulato... | 05/01/2001 |
| 6214673 | Process for forming vertical semiconductor device having increased source contact area A process for forming a vertical semiconductor device having increased source contact area comprises forming a gate and a well region in a silicon substrate. Using dopant of a second conductivity type, a shallow source region is formed in the well region,... | 04/10/2001 |
| 6165848 | Method for the production of a MOS-controlled power semiconductor component The invention relates to a method for the production of a MOS-controlled power semiconductor component (30), which power semiconductor component (30) comprises, in a common substrate (31), a plurality of component cells which are arranged next to one anot... | 12/26/2000 |
| 6037628 | Semiconductor structures with trench contacts Semiconductor structures such as the trench and planar MOSFETs (UMOS), trench and planar IGBTs and trench MCTs using trenches to establish a conductor. Improved control of the parasitic transistor in the trench MOSFET is also achieved and cell size and pi... | 03/14/2000 |
| 5910668 | Method of making a insulated gate bipolar transistor with high-energy P+ implant and silicon-etch contact An improved insulated gate bipolar transistor (IGBT) device structure and a method for fabricating such a device. This structure uses self-aligned and substantially undiffused successive N+ and P+ implants. The P+ implant is at high energy, which forms a ... | 06/08/1999 |
| 5891776 | Methods of forming insulated-gate semiconductor devices using self-aligned trench sidewall diffusion techniques A method of forming an insulated gate semiconductor device includes the steps of patterning an insulated gate electrode on a face of a substrate containing a first conductivity type region and forming a trench at the face using the gate electrode as a mas... | 04/06/1999 |
| 5879968 | Process for manufacture of a P-channel MOS gated device with base implant through the contact window An MOS-gated power semiconductor device is formed by a process that uses a reduced number of masking steps and minimizes the number of critical alignments. A first photolithographic masking step defines the body or channel region and the source region of ... | 03/09/1999 |
| 5869864 | Field effect controlled semiconductor component A semiconductor component having a body with an upper surface, a base zone having a portion adjoining the upper surface of the semiconductor body, at least one source zone embedded in the base zone, at least one gate electrode lying parallel to the upper ... | 02/09/1999 |
| 5843796 | Method of making an insulated gate bipolar transistor with high-energy P+ i m An improved insulated gate bipolar transistor (IGBT) device structure and a method for fabricating such a device. This structure uses self-aligned and substantially undiffused successive N+ and P+ implants. The P+ implant is at high energy, which forms a ... | 12/01/1998 |
| 5801417 | Self-aligned power MOSFET device with recessed gate and source A recessed gate power MOSFET is formed on a substrate (20) including a P-body layer (26), N-drain layer (24) and optional P+ layer (22) for IGBT. A trenching protective layer (30) formed on the substrate upper surface (28) is patterned to define exposed a... | 09/01/1998 |
| 5763902 | Insulated gate bipolar transistor having a trench and a method for production thereof An insulated gate bipolar transistor comprises a drain which supports a highly doped p-type substrate layer; a low doped n-type drift layer supported over the substrate layer; a base layer supported over the drift layer including a trench extending into t... | 06/09/1998 |
| 5583060 | Method for manufacturing field effect controlled semiconductor components The base zones of MOSFETs and IGBTs are generated by implanting dopants of the second conductivity type into the surface of a first layer of the first conductivity type, and a second layer of the first conductivity type is deposited thereon. During the de... | 12/10/1996 |
| 5528058 | IGBT device with platinum lifetime control and reduced gaw For IGBT, MCT or like devices, the substrate is formed with P+, N+ and N- layers and PN diffusions to define body and source regions in the N-layer and a MOS-gated channel at the upper surface. The N-layer is sized and doped (~1014 /cm3 | 06/18/1996 |
| 5408117 | Semiconductor device and method of fabricating the same A semiconductor device comprises a first conductivity type semiconductor layer and a second conductivity type well region which is formed on the semiconductor layer. The well region includes a first semiconductor region of a first depth and a second semic... | 04/18/1995 |
| 5283201 | High density power device fabrication process A recessed gate power MOSFET is formed on a substrate (20) including a P-body layer (26), N-drain layer (24) and optional P+ layer (22) for IGBT. A trenching protective layer (30) formed on the substrate upper surface (28) is patterned to define exposed a... | 02/01/1994 |
| 5283202 | IGBT device with platinum lifetime control having gradient or profile tailored platinum diffusion regions For IGBT, MCT or like devices, the substrate is formed with P+, N+ and N- layers and PN diffusions to define body and source regions in the N-layer and a MOS-gated channel at the upper surface. The N-layer is sized and doped (~1014 /cm3 | 02/01/1994 |
| 5262336 | IGBT process to produce platinum lifetime control For IGBT, MCT or like devices, the substrate is formed with P+, N+ and N- layers and PN diffusions to define body and source regions in the N-layer and a MOS-gated channel at the upper surface. The N-layer is sized and doped (~1014 /cm3 | 11/16/1993 |
| 5178370 | Conductivity modulated insulated gate semiconductor device A vertical conducting insulating gate bipolar transistor having an emitter region formed in a base region wherein the base region is not shorted to the emitter is provided. The emitter and base regions are formed in an upper portion of a lightly doped sem... | 01/12/1993 |
| 5008720 | Semiconductor device with stepped well A semiconductor device comprises a first conductivity type semiconductor layer and a second conductivity type well region which is formed on the semiconductor layer. The well region includes a first semiconductor region of a first depth and a second semic... | 04/16/1991 |
| 4809047 | Insulated-gate semiconductor device with improved base-to-source electrode short and method of fabricating said short Insulated-gate semiconductor devices, such as MOSFETs or IGTs, include an implant shorting region adjoining both base and source regions with the implant shorting region being conductively coupled to the source electrode so as to implement a base-to-sourc... | 02/28/1989 |
