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| Number | Title | Issue Date |
| 7335585 | Method for preventing the formation of a void in a bottom anti-reflective coating filling a via hole A method for manufacturing a semiconductor device which, on performing a via first Dual Damascene process, inhibits or prevents the formation of a void in a bottom anti-reflective coating filling a via hole. The method typically includes the steps of forming a botto... | 02/26/2008 |
| 7256146 | Method of forming a ceramic diffusion barrier layer The present invention comprises an interconnect structure including a metal, interlayer dielectric and a ceramic diffusion barrier formed therebetween, where the ceramic diffusion barrier has a composition SivNwCxOyHz... | 08/14/2007 |
| 7189663 | Organic semiconductor device having an active dielectric layer comprising silsesquioxanes An organic field effect transistor (FET) is described with an active dielectric layer comprising a low-temperature cured dielectric film of a liquid-deposited silsesquioxane precursor. The dielectric film comprises a silsesquioxane having a dielectric constant of gr... | 03/13/2007 |
| 7148108 | Method of manufacturing semiconductor device having step gate Disclosed herein is a method of manufacturing a semiconductor device having a step gate, which can improve the refresh characteristics of the device. The method comprises the steps of: forming on a silicon substrate having active and field regions a first hard mask ... | 12/12/2006 |
| 6677680 | Hybrid low-k interconnect structure comprised of 2 spin-on dielectric materials A metal wiring plus low-k dielectric interconnect structure of the dual damascene-type is provided wherein the conductive metal lines and vias are built into a hybrid low-k dielectric which includes two spun-on dielectrics that have different atomic compo... | 01/13/2004 |
| 6649503 | Methods of fabricating integrated circuit devices having spin on glass (SOG) insulating layers and integrated circuit devices fabricated thereby Methods are provided for forming integrated circuit devices. A spin on glass (SOG) insulating layer is formed on an integrated circuit substrate. The SOG insulating layer includes sidewalls that define contact holes therein and spacers are formed on the s... | 11/18/2003 |
| 6638358 | Method and system for processing a semiconductor device The present invention is a method and system for processing a semiconductor device, the semiconductor device comprising at least two gate stacks and a spacer gap. The method and system comprise utilizing a spin-on technique at the transistor device level ... | 10/28/2003 |
| 6633082 | Semiconductor device and method for manufacturing the semiconductor device A semiconductor device is provided and contains a substrate, a first wiring layer, a first oxide film, a dielectric film, a first nitrogen layer, a second wiring layer, a via hole, and a second nitrogen layer. The first wiring layer is formed on the subst... | 10/14/2003 |
| 6632748 | Composition for preparing substances having nano-pores The present invention provides a composition for preparing substances having nano-pores, said composition comprising cyclodextrin derivative, thermo-stable organic or inorganic matrix precursor, and solvent for dissolving said two solid components. There ... | 10/14/2003 |
| 6627533 | Method of manufacturing an insulation film in a semiconductor device A method of manufacturing an insulating film in a semiconductor device is disclosed. The method comprises the steps of forming a SOD film on the entire structure to fill any distance between conductive layer patterns and after performing a curing process,... | 09/30/2003 |
| 6623711 | Siloxane-based resin and method for forming insulating film between interconnect layers in semiconductor devices by using the same Disclosed herein are siloxane-based resins prepared by hydrolyzing and polycondensing cyclic and/or cage-shape siloxane compounds, optionally with at least one silane compound, in an organic solvent in the presence of a catalyst and water. Also, disclosed... | 09/23/2003 |
| 6472335 | Methods of adhesion promoter between low-K layer and underlying insulating layer The present invention provides a method improving the adhesion between inter metal dielectric (IMD) layers by performing a HF dip etch to treat the surface of an oxide, silicon nitride or Silicon oxynitride insulating layer before an overlying low-K layer... | 10/29/2002 |
| 6472751 | H2 diffusion barrier formation by nitrogen incorporation in oxide layer A dielectric interlayer is formed over a semiconductor substrate comprising at least one active region. The exposed upper surface of the dielectric interlayer is treated with nitrogen to form a nitrided barrier layer thereon. At least one hydrogen-contain... | 10/29/2002 |
| 6455443 | Method of fabricating low-dielectric constant interlevel dielectric films for BEOL interconnects with enhanced adhesion and low-defect density A substantially defect-free, low-k dielectric film having improved adhesion is provided by (a) applying a silane coupling agent containing at least one polymerizable group to a surface of a substrate so as to provide a substantially uniform coating of sai... | 09/24/2002 |
| 6447846 | Electrically insulating thin-film-forming resin composition and method for forming thin film therefrom An electrically insulating thin-film-forming resin composition comprising (A) a hydrogen silsesquioxane resin, (B) a solvent-soluble polymer, and (C) a solvent; and a method for forming an electrically insulating thin film therefrom.... | 09/10/2002 |
| 6444136 | Fabrication of improved low-k dielectric structures Fabrication of improved low-k dielectric structures is disclosed. Low-k dielectric structures are fabricated while overcoming the otherwise existing problems associated with the use of low-k dielectric materials. In one embodiment, the physical properties... | 09/03/2002 |
| 6420278 | Method for improving the dielectric constant of silicon-based semiconductor materials An ultra-large scale integrated circuit is manufactured by using silicon-based, low dielectric constant materials in which the dielectric constant has been reduced by spinning on the dielectric to silicon wafers, eliminating soft bake steps, and heating t... | 07/16/2002 |
| 6407009 | Methods of manufacture of uniform spin-on films This invention describes improved apparatus and methods for spin-on deposition of semiconductor thin films. The improved apparatus provides for controlled temperature, pressure and gas compositions within the deposition chamber. The improved methods compr... | 06/18/2002 |
| 6388309 | Apparatus and method for manufacturing semiconductors using low dielectric constant materials An ultra-large scale integrated circuit is manufactured by using silicon-based, low dielectric constant materials which are spin-coated, dried, cured, and capped in-situ in chemical vapor deposition equipment. The low dielectric constant material is spun ... | 05/14/2002 |
| 6387825 | Solution flow-in for uniform deposition of spin-on films This invention describes improved apparatus and methods for spin-on deposition of thin films applicable to the manufacture of semiconductor devices. The improved apparatus provides for controlled temperature, pressure and gas compositions within the depos... | 05/14/2002 |
| 6348736 | In situ formation of protective layer on silsesquioxane dielectric for dual damascene process Resist developers can attack some advanced dielectric materials such as silsesquioxane materials which can be used as an insulator between a surface of an integrated circuit chip and wiring layers formed on the surface of the dielectric material. A first ... | 02/19/2002 |
| 6303524 | High temperature short time curing of low dielectric constant materials using rapid thermal processing techniques A method for curing low k dielectric materials uses very short, relatively high temperature cycles instead of the conventionally used (lower temperature/longer time) thermal cycles. A substrate, such as a semiconductor wafer, coated with a layer of coatin... | 10/16/2001 |
| 6251805 | Method of fabricating semiconductor device A hydrogen silsesquloxane resin film is formed flat by spin-coating or another such method on the surface of a semiconductor substrate or another such treatment wafer 38, after which the above-mentioned resin film is subjected to a heat treatment in an in... | 06/26/2001 |
| 6225240 | Rapid acceleration methods for global planarization of spin-on films This invention describes improved apparatus and methods for spin-on deposition of semiconductor thin films. The improved apparatus provides for controlled temperature, pressure and gas compositions within the deposition chamber. The improved methods compr... | 05/01/2001 |
| 6210749 | Thermally stable dielectric coatings This invention pertains to a method for producing thermally stable multi-layer coatings and the coatings produced therefrom. The multi-layer coating is comprised of a first coating produced from hydrogen silsesquioxane having a thickness of 1.25 to 2.25 Î... | 04/03/2001 |
| 6200913 | Cure process for manufacture of low dielectric constant interlevel dielectric layers This invention comprises improvements in the ways in which spin-on dielectric layers are cured. A semiconductor wafer is coated with a precursor for a spin-on dielectric material, and after the solution is thinned and evened, the wafer is placed in a curi... | 03/13/2001 |
| 6197703 | Apparatus and method for manufacturing semiconductors using low dielectric constant materials An ultra-large scale integrated circuit is manufactured by using silicon-based, low dielectric constant materials which are spin-coated, dried, cured, and capped in-situ in chemical vapor deposition equipment. The low dielectric constant material is spun ... | 03/06/2001 |
| 6194328 | H2 diffusion barrier formation by nitrogen incorporation in oxide layer A dielectric interlayer is formed over a semiconductor substrate comprising at least one active region. The exposed upper surface of the dielectric interlayer is treated with nitrogen to form a nitrided barrier layer thereon. At least one hydrogen-contain... | 02/27/2001 |
| 6169039 | Electron bean curing of low-k dielectrics in integrated circuits An integrated circuit and a method of forming an integrated circuit is described. The integrated circuit includes a silicon substrate, a dielectric stack formed on the silicon substrate, and conductive metal lines overlying the silicon substrate. A first ... | 01/02/2001 |
| 6153514 | Self-aligned dual damascene arrangement for metal interconnection with low k dielectric constant materials and nitride middle etch stop layer A method of forming a self-aligned dual damascene structure in a semiconductor device arrangement forms a first low k dielectric material over an underlying metal interconnect layer, such as a copper interconnect layer. A nitride etch stop layer is formed... | 11/28/2000 |
| 6153512 | Process to improve adhesion of HSQ to underlying materials A process for forming an intermetal dielectric, (IMD), layer, comprised of an overlying silicon oxide layer, and an underlying low k dielectric layer, such as hydrogen silsesquioxane, (HSQ), has been developed. The process features the use of a series of ... | 11/28/2000 |
| 6140221 | Method for forming vias through porous dielectric material and devices formed thereby A semiconductor device has a device layer, a conductive structure, such as a conductive line, disposed over the device layer, and a porous dielectric layer disposed over the device layer and the conductive structure. At least one via is formed through the... | 10/31/2000 |
| 6136729 | Method for improving semiconductor dielectrics An ultra-large scale integrated circuit is manufactured by using silicon-based, low dielectric materials on a wafer in which the hydrophobic nature of the dielectric materials is improved by relative low temperature heating in a vacuum or inert atmosphere... | 10/24/2000 |
| 6124216 | Method of making intermetal dielectric layers having a low dielectric constant A method of forming a low-k dielectric insulating layer includes forming the dielectric insulating layer and then removing hydrogen bonds in the dielectric insulating layer. The dielectric layer as formed is preferably a HSQ film which contains the struct... | 09/26/2000 |
| 6114186 | Hydrogen silsesquioxane thin films for low capacitance structures in integrated circuits An improved method is provided for integrating HSQ into integrated circuit structures and processes, especially those requiring multiple levels of interconnect lines. In a preferred embodiment, interconnect lines 14 are first patterned and etched on a sub... | 09/05/2000 |
| 6087724 | HSQ with high plasma etching resistance surface for borderless vias HSQ is employed for gap filling patterned metal layers. The surface of the deposited HSQ gap fill layer is modified to decrease its plasma etching rate. Embodiments include modifying the HSQ surface by exposure to a plasma, such as a nitrogen-containing p... | 07/11/2000 |
| 6084290 | HSQ dielectric interlayer The use of HSQ as a dielectric interlayer without cracking is achieved by depositing HSQ on a planarized dielectric layer, such as a silicon oxide derived from TEOS or silane. Embodiments include depositing a first HSQ gap fill layer on a patterned metal ... | 07/04/2000 |
| 6083850 | HSQ dielectric interlayer The use of HSQ as a dielectric interlayer without cracking is achieved by depositing HSQ on a planarized dielectric layer, such as a silicon oxide derived from TEOS or silane. Embodiments include depositing a first HSQ gap fill layer on a patterned metal ... | 07/04/2000 |
| 6083851 | HSQ with high plasma etching resistance surface for borderless vias HSQ is employed for gap filling patterned metal layers. The surface of the deposited HSQ gap fill layer is modified to decrease its plasma etching rate. Embodiments include modifying the HSQ surface by exposure to a plasma, such as a nitrogen-containing p... | 07/04/2000 |
| 6080526 | Integration of low-k polymers into interlevel dielectrics using controlled electron-beam radiation A process for the preparation of substrates used in the manufacture of integrated circuits wherein spin-on low dielectric constant (low-k) polymer films are applied on semiconductor substrates. A non-etchback processing of spin-on low-k polymer films, wit... | 06/27/2000 |
