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| Number | Title | Issue Date |
| 7432137 | Method of manufacturing thin film transistor A method of manufacturing a thin film transistor includes forming a gate electrode on a substrate; forming a gate insulating film on the gate electrode; forming a semiconductor layer on the gate insulating film; forming a bank including a first bank portion and a se... | 10/07/2008 |
| 7429534 | Etching a nitride-based heterostructure An improved solution for producing nitride-based heterostructure(s), heterostructure device(s), integrated circuit(s) and/or Micro-Electro-Mechanical System(s) is provided. A nitride-based etch stop layer that includes Indium (In) is included in a heterostructure. A... | 09/30/2008 |
| 7413958 | GaN-based permeable base transistor and method of fabrication An etched grooved GaN-based permeable-base transistor structure is disclosed, along with a method for fabrication of same. ... | 08/19/2008 |
| 7365017 | Method for finishing metal line for semiconductor device A method for finishing a metal line for a semiconductor device is disclosed, in which polymer generated when forming the metal line including aluminum and its alloy is effectively removed and the metal line is prevented from being eroded. A chlorine radical and a ch... | 04/29/2008 |
| 7344954 | Method of manufacturing a capacitor deep trench and of etching a deep trench opening A substrate is provided having an oxide layer, a first nitride-silicon, a STI, and a second nitride-silicon. A pattern poly-silicon layer on the second nitride-silicon layer is etched to form a deep trench opening. Etching the pattern poly-silicon layer also deepens... | 03/18/2008 |
| 7341935 | Alternative interconnect structure for semiconductor devices A semiconductor interconnect structure includes an organic and/or photosensitive etch buffer layer disposed over a contact surface. The structure further provides an interlevel dielectric formed over the etch buffer layer. A method for forming an interconnect struct... | 03/11/2008 |
| 7335980 | Hardmask for reliability of silicon based dielectrics The present invention provides a hardmask that is located on a surface of a low k dielectric material having at least one conductive feature embedded therein. The hardmask includes a lower region of a hermetic oxide material located adjacent to the low k dielectric ... | 02/26/2008 |
| 7148114 | Process for patterning high-k dielectric material A method of patterning a layer of high-k dielectric material is provided, which may be used in the fabrication of a semiconductor device. A first etch is performed on the high-k dielectric layer. A portion of the high-k dielectric layer being etched with the first e... | 12/12/2006 |
| 6686283 | Shallow trench isolation planarization using self aligned isotropic etch A method for forming planar isolation structures for integrated circuits. A etch barrier is formed over the isolation fill material and an etch back is performed to remove material above unetched portions of the substrate. The exposed fill material is etc... | 02/03/2004 |
| 6642147 | Method of making thermally stable planarizing films Disclosed is a method of protecting semiconductor areas while exposing a structures for processing on a semiconductor surface, the method comprising depositing a planarizing high density plasma film of a silicon compound, selected from the group silicon o... | 11/04/2003 |
| 6639266 | Modifying material removal selectivity in semiconductor structure development Container structures for use in integrated circuits and methods of their manufacture without the use of mechanical planarization such as chemical-mechanical planarization (CMP), thus eliminating CMP-induced defects and variations. The methods utilize loca... | 10/28/2003 |
| 6616855 | Process to reduce surface roughness of low K damascene Low K dielectrics, such as porous silica, present a problem during damascene processing in that the trench floor tends to be rough, thus requiring a thicker than desired barrier layer. This problem has been overcome by fully covering the trench floor with... | 09/09/2003 |
| 6617241 | Method of thick film planarization Planarization of the top surfaces of layers that are more than about a micron thick is beset with problems not encountered in thinner layers. These problems have been overcome by means of a process that, initially allows the formation of `horns` in the su... | 09/09/2003 |
| 6472271 | Planarization method of memory unit of flash memory The present invention discloses a planarization method of memory unit of a flash memory, wherein a patterned polysilicon layer and a silicon nitride layer are formed in turn on a semiconductor substrate. A silicon dioxide layer is then deposited by the HD... | 10/29/2002 |
| 6432827 | ILD planarization method The present invention provides a method of planarization for an inter layer dielectric of an EDRAM. The method comprises defining a periphery circuit region and a memory array area on a semiconductor wafer of the EDRAM, and forming a plurality of MOS tran... | 08/13/2002 |
| 6403484 | Method to achieve STI planarization A method of forming shallow trench isolations is described. A plurality of isolation trenches are etched through a first etch stop layer into the underlying semiconductor substrate. An oxide layer is deposited over the first etch stop layer and within the... | 06/11/2002 |
| 6395620 | Method for forming a planar surface over low density field areas on a semiconductor wafer A method for forming a planar surface over low density fields on a semiconductor wafer that has a contoured front face with a low region between high points. In accordance with one embodiment of the method, a fill layer is deposited over the front face to... | 05/28/2002 |
| 6391718 | Planarization method for flash memory device A method to planarize a flash memory device, wherein the method is applied on a substrate having a polysilicon layer and a cap layer sequentially formed thereon. Thereafter, the cap layer and the polysilicon layer are patterned to form the peripheral circ... | 05/21/2002 |
| 6387808 | Method of correcting topographical effects on a micro-electronic substrate A method of correcting topographical effects on a microelectronic substrate, the method comprising the steps consisting in depositing a layer of resin on the structure to be planarized having topography in relief surrounded by isolation zones, and subject... | 05/14/2002 |
| 6380068 | Method for planarizing a flash memory device A method to planarize a flash memory device, wherein the method is applied on a substrate having a polysilicon layer and a cap layer sequentially formed thereon. Thereafter, the cap layer and the polysilicon layer are patterned to form the peripheral circ... | 04/30/2002 |
| 6368906 | Method of planarization using selecting curing of SOG layer A method for planarizing an interlayer dielectric layer formed on a semiconductor substrate having a step, using wet etch, by depositing first and second layers on the semiconductor substrate and selectively curing the second layer in the lower area using... | 04/09/2002 |
| 6323102 | Method of manufacturing a semiconductor device A method of manufacturing a semiconductor device having a microminiture trench isolation in which an insulating film is embedded by an HDP-CVD method comprising: a step of pre-planarization by conducting a dry etching selectively with respect to the insul... | 11/27/2001 |
| 6281112 | Structure of interlayer insulator film and method for planarization of interlayer insulator film An interlayer insulator film in a semiconductor device comprises a BPSG film formed to cover a circuit pattern formed on a semiconductor substrate, and a ladder structure SOG film having a ladder structure in a molecular structure, to cover the BPSG film.... | 08/28/2001 |
| 6274509 | Global planarization method for inter-layer-dielectric and inter-metal dielectric A method of planarizing a layer of dielectric material is disclosed herein that is particularly suitable for planarizing inter-layer-dielectrics (ILD) or inter-metal-dielectrics (IMD). The planarizing method comprises the steps of depositing a layer of sa... | 08/14/2001 |
| 6107187 | Method for forming a semiconductor device An opening (24) is formed in a substrate (20). A first layer (30) is formed over the substrate (20) and the feature opening (24). A second layer (40) is formed over the first layer (30) and then the second layer is removed until exposing portions (50) of ... | 08/22/2000 |
| 6069056 | Method of forming isolation structure A method of forming an isolation region of a semiconductor device, includes the steps of forming a first insulating film on a substrate; defining a plurality of isolation regions on the first insulating film; removing portions of the first insulating film... | 05/30/2000 |
| 6063702 | Global planarization method for inter level dielectric layers using IDL blocks The present invention provides a method of manufacturing of planarizing an insulating layer using a reduced size reversed interconnect mask and an etch stop layer. Spaced interconnections 22 are provided over the semiconductor substrate 10. An etch stop l... | 05/16/2000 |
| 6025270 | Planarization process using tailored etchback and CMP An improved and new method for forming a planarized integrated cirsuit structure has been developed. The method uses a combination of etchback and chemical/mechanical polishing (CMP), in which the etchback process uses a tailored mask to compensate for no... | 02/15/2000 |
| 6020256 | Method of integrated circuit fabrication Dielectric planarization is achieved by Defocus and under exposure of photoresist. The photoresist may be etched at the same rate as the dielectric, thereby yielding a smooth or planarized dielectric.... | 02/01/2000 |
| 6015757 | Method of oxide etching with high selectivity to silicon nitride by using polysilicon layer A new method for planarization of shallow trench isolation is disclosed by using a polysilicon layer to prevent trench formed in a silicon nitride layer. The formation of the shallow trench isolation described herein includes a pad layer and a silicon nit... | 01/18/2000 |
| 5994231 | Process for depositing a stratified dielectric structure for enhancing the planarity of semiconductor electronic devices A method of depositing a layered dielectric structure to improve the planarity of electronic devices which include a plurality of active elements having gate regions laid across the substrate as discrete parallel lines, such as the bit lines of memory cel... | 11/30/1999 |
| 5965939 | Semiconductor device and a method of manufacture A semiconductor device having a closed step portion and a global step portion including an insulating layer having a planarized surface on the global step portion is provided. A dummy pattern is formed by forming an insulating layer on the global step por... | 10/12/1999 |
| 5958797 | Planarization of a patterned structure on a substrate using an ion implantation-assisted wet chemical etch A method for planarizing a patterned structure on a top surface of a substrate comprises the steps of depositing an insulating layer on the patterned structure, implanting ionized atoms of a predetermined depth onto the surface of the insulating layer, co... | 09/28/1999 |
| 5946591 | Method of making a semiconductor device having a flat surface A manufacturing method for semiconductor devices such as dynamic RAM, etc. which removes the layer part more on the high position than an arbitrary position on a step forming a gradation by just a prescribed thickness when flattening a layer with a gradat... | 08/31/1999 |
| 5926723 | Generation of a loose planarization mask having relaxed boundary conditions for use in shallow trench isolation processes A method of forming an improved planarization mask for shallow trench isolation process area in integrated circuit manufacturing is disclosed. The planarization mask is generated automatically by using actual mask data as a reference. The invention disclo... | 07/20/1999 |
| 5925575 | Dry etching endpoint procedure to protect against photolithographic misalignments A process for forming a planarized, insulator, or silicon oxide filled shallow trench has been developed. The process features a hybrid planarization procedure, comprised of an initial dry etching cycle, used to remove all but about 100 to 500 Angstroms o... | 07/20/1999 |
| 5926722 | Planarization of shallow trench isolation by differential etchback and chemical mechanical polishing A new method for planarization of shallow trench isolation is disclosed by using wet selective etching. The formation of the shallow trench isolation described herein includes a pad layer, a silicon nitride layer formed on a semiconductor substrate. A PE-... | 07/20/1999 |
| 5840619 | Method of making a semiconductor device having a planarized surface An object of the present invention is to completely reduce a difference in level in a short time at a convex pattern spreading horizontally on a large scale and obtain a semiconductor device having a planarized surface. An insulating film is formed on a s... | 11/24/1998 |
| 5723380 | Method of approach to improve metal lithography and via-plug integration A method is described wherein topography of semiconductor wafer surfaces is improved. This is accomplished by introducing a specific planarization technique after the deposition of the first level of metal. It is shown further that the technique involves ... | 03/03/1998 |
| 5488007 | Method of manufacture of a semiconductor device A method for manufacturing a semiconductor device having a closed step portion and a global step portion including an insulating layer is provided. A dummy pattern is formed by forming an insulating layer on the global step portion and then patterning thr... | 01/30/1996 |
