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| Number | Title | Issue Date |
| 7439118 | Method of manufacturing semiconductor integrated circuit A method of manufacturing a semiconductor integrated circuit including a logic part and a memory array part, the logic part having N-type and P-type FETs, and the memory array part having N-type and P-type FETs, includes the steps of forming N-type and P-type FETs c... | 10/21/2008 |
| 7432217 | Method of achieving uniform length of carbon nanotubes (CNTS) and method of manufacturing field emission device (FED) using such CNTS In a method of achieving uniform lengths of Carbon NanoTubes (CNTs) and a method of manufacturing a Field Emission Device (FED) using such CNTs, an organic film is coated to cover CNTs formed on a predetermined material layer. The organic film is etched to a predete... | 10/07/2008 |
| 7411220 | Semiconductor light emitting device and manufacturing method thereof A semiconductor light emitting device can have stable electric characteristics and can emit light with high intensity from a substrate surface. The device can include a transparent substrate and a semiconductor layer on the substrate. The semiconductor layer can inc... | 08/12/2008 |
| 7396733 | Method for manufacturing semiconductor substrate and method for manufacturing semiconductor device A method for manufacturing a semiconductor substrate, including: forming a first semiconductor layer on a semiconductive base; forming a second semiconductor layer, having a smaller etching selection ratio than that of the first semiconductor layer, on the first sem... | 07/08/2008 |
| 7393768 | Etching of structures with high topography The present invention relates to a method for the patterning of a stack of layers on a surface with high topography. A method of the present invention can be used for gate patterning for multiple Gate FETs (MuGFETs), for patterning of the control gate in non-volatil... | 07/01/2008 |
| 7378341 | Automatic process control of after-etch-inspection critical dimension Automatic process control of after-etch-inspection critical dimension. A dielectric layer is deposited over a substrate and is then planarized to a first thickness. A cap oxide layer having a second thickness is deposited, wherein the combination of the first thickn... | 05/27/2008 |
| 7365017 | Method for finishing metal line for semiconductor device A method for finishing a metal line for a semiconductor device is disclosed, in which polymer generated when forming the metal line including aluminum and its alloy is effectively removed and the metal line is prevented from being eroded. A chlorine radical and a ch... | 04/29/2008 |
| 7348231 | Methods of fabricating semiconductor devices having insulating layers with differing compressive stresses Methods of fabricating semiconductor devices are provided. An NMOS transistor and a PMOS transistor are provided on a substrate. The NMOS transistor is positioned on an NMOS region of the substrate and the PMOS transistor is positioned on a PMOS region of the substr... | 03/25/2008 |
| 7341935 | Alternative interconnect structure for semiconductor devices A semiconductor interconnect structure includes an organic and/or photosensitive etch buffer layer disposed over a contact surface. The structure further provides an interlevel dielectric formed over the etch buffer layer. A method for forming an interconnect struct... | 03/11/2008 |
| 7300827 | Method of manufacturing a thin film transistor substrate and stripping composition A method of manufacturing a thin film transistor substrate includes forming a transistor thin layer pattern, forming a protecting layer, forming a photoresist film, forming a pixel electrode and a conductive layer that are separated from each other, stripping a phot... | 11/27/2007 |
| 7294552 | Electrical contact for a MEMS device and method of making A method for making a subsurface electrical contact on a micro-electrical-mechanical-systems (MEMS) device. The contact is formed by depositing a layer of polycrystalline silicon onto a surface within a cavity buried under a device silicon layer. The polycrystalline... | 11/13/2007 |
| 7285497 | Mask, method for manufacturing a mask, method for manufacturing an electro-optical device, and electronic equipment A mask includes a silicon member, and a portion defining an opening penetrating the silicon member; and the corner of the opening is rounded. ... | 10/23/2007 |
| 7271063 | Method of forming FLASH cell array having reduced word line pitch A method of forming a NAND Flash memory device includes forming a control gate polysilicon layer over a substrate, forming a mask layer over the control gate polysilicon layer, the mask layer including a mask pattern defining a plurality of spaced word lines of the ... | 09/18/2007 |
| 7259076 | High-density SOI cross-point memory fabricating method A method for fabricating a high-density silicon-on-insulator (SOI) cross-point memory array and an array structure are provided. The method includes the following steps: selectively forming a hard mask on an SOI substrate, defining memory areas, active device areas,... | 08/21/2007 |
| 7224026 | Nanoelectronic devices and circuits Diode devices with superior and pre-settable characteristics and of nanometric dimensions, comprise etched insulative lines (8, 16, 18) in a conductive substrate to define between the lines charge carrier flow paths, formed as elongate channels (20) at... | 05/29/2007 |
| 6703318 | Method of planarizing a semiconductor die A method of CMP planarizing a silicon dioxide layer on a silicon nitride in the semiconductor die is disclosed. A wafer has a plurality substantially identical semiconductor dies defined on the wafer. Each of the dies is separated from one another by a sc... | 03/09/2004 |
| 6682985 | Semiconductor device and manufacturing method thereof A semiconductor device as well as a method of manufacturing a semiconductor device wherein a wide trench separation band is formed without causing the scooping out of the silicon substrate can be gained. The process is provided with the step of forming a multi... | 01/27/2004 |
| 6653722 | Method for applying uniform pressurized film across wafer A method of manufacturing semiconductor devices using an improved planarization process for the planarization of the surfaces of the wafer on which the semiconductor devices are formed. The improved planarization process includes the formation of a flat p... | 11/25/2003 |
| 6639285 | Method for fabricating a semiconductor device A method for making a semiconductor device is provided. The method allows for depositing a layer of a doped dielectric. The method further allows for executing plasma etching so that one or more etchant gases flow over the layer of doped dielectric. A red... | 10/28/2003 |
| 6624044 | Method for manufacturing semiconductor device having trench filled with polysilicon First, a trench of a semiconductor substrate is filled with a polysilicon film deposited on the surface of the semiconductor substrate. A selective thin film having etching selectivity with respect to the polysilicon film is formed on the polysilicon film... | 09/23/2003 |
| 6620534 | Film having enhanced reflow characteristics at low thermal budget A method of forming a film having enhanced reflow characteristics at low thermal budget is disclosed, in which a surface layer of material is formed above a base layer of material, the surface layer having a lower melting point than the base layer. In thi... | 09/16/2003 |
| 6617259 | Method for fabricating semiconductor device and forming interlayer dielectric film using high-density plasma A method for fabricating a semiconductor device and forming an insulating film used therein, includes forming an isolation insulating film on a semiconductor wafer and forming gates, separated by gaps having a predetermined distance, on an active region. ... | 09/09/2003 |
| 6613688 | Semiconductor device and process for generating an etch pattern A model-based approach for generating an etch pattern to decrease topographical uniformity involves placing reverse dummy features (50, 52, 70) in a region of a semiconductor substrate (40, 60) according to the topography of the region and adjacent region... | 09/02/2003 |
| 6610573 | Method for forming a single wiring level for transistors with planar and vertical gates on the same substrate A memory cell comprises a region containing one or more vertical pass transistor, and a support region containing, e.g. one or more planar transistors. During processing, a polysilicon layer is formed for the planar devices gate. The polysilicon layer is ... | 08/26/2003 |
| 6593238 | Method for determining an endpoint and semiconductor wafer A method for determining an endpoint during chemical-mechanical polishing of a semiconductor wafer (100, 200) is disclosed. The method comprises the steps of depositing on a first layer (106, 206) to be polished a second layer (108, 208), the physical pro... | 07/15/2003 |
| 6593241 | Method of planarizing a semiconductor device using a high density plasma system A method for planarizing a layer of material on a semiconductor device is disclosed, which planarizes a layer on a semiconductor device using a high density plasma system, and uses a sacrificial layer having a desirable etch to deposition rate. Additional... | 07/15/2003 |
| 6518172 | Method for applying uniform pressurized film across wafer A method of manufacturing semiconductor devices using an improved planarization processes for the planarization of the surfaces of the wafer on which the semiconductor devices are formed. The improved planarization process includes the formation of a flat... | 02/11/2003 |
| 6518114 | Method of forming an insulating zone The invention relates to a method of forming an insulating zone (14) around an active zone (12) in a semiconductor substrate, which method includes the following steps: forming a groove around an active zone (12) in the substrate; and filling the groove w... | 02/11/2003 |
| 6479369 | Shallow trench isolation (STI) and method of forming the same A method of forming a shallow trench isolation, includes the steps, in sequence, of (a) forming a mask pattern on a silicon substrate, the mask pattern being made of a silicon dioxide layer and a silicon nitride layer, (b) forming a trench in the silicon ... | 11/12/2002 |
| 6444581 | AB etch endpoint by ABFILL compensation A method for determining the AB etch endpoint during an silicon trench isolation fabrication process requires the introduction into the STI design a sufficient quantity of "dummy" diffusion structures that provide a strong endpoint signal during normal ST... | 09/03/2002 |
| 6437444 | Interlayer dielectric with a composite dielectric stack A method of forming an interlayer dielectric on a semiconductor device is disclosed. First, a phosphorous doped oxide layer is deposited on the semiconductor device to fill gaps and provide phosphorous for gettering. Then, an undoped oxide layer is deposi... | 08/20/2002 |
| 6432797 | Simplified method to reduce or eliminate STI oxide divots A method for forming shallow trench isolation wherein oxide divots at the edge of the isolation and active regions are reduced or eliminated is described. A trench is etched into a semiconductor substrate. An oxide layer is deposited overlying the semicon... | 08/13/2002 |
| 6423640 | Headless CMP process for oxide planarization A method for planarizing an oxide surface and removing dishing or erosion defect from a semiconductor wafer. An apparatus for carrying out the planarization process on a semiconductor wafer is further described. In the method, a wafer that has metal resid... | 07/23/2002 |
| 6417073 | Method for forming element isolating region There is provided a method for forming a Shallow Trench Isolation (STI) easy to suppress an occurrence of the debot even when the micro-scratch is present. A silicon oxide film made of an organic Spin-On-Glass (SOG) film is formed on a surface of a silico... | 07/09/2002 |
| 6399506 | Method for planarizing an oxide layer A method of planarizing an oxide layer. The method includes performing an isotropic chemical dry etching operation using a nitrogenous processing gas. Furthermore, oxygen can also be added to the nitrogenous processing gas during the isotropic chemical dr... | 06/04/2002 |
| 6391781 | Method of making a semiconductor device A method of manufacturing a semiconductor device using a shallow trench isolation (STI) process comprises the steps of depositing a Si3N4 film (3) by a chemical vapor deposition (CVD) process, polishing a CVD oxide film (6) by a chemical mechanical polish... | 05/21/2002 |
| 6388934 | Semiconductor memory device operating at high speed with low current consumption Column select gates are provided to normal bit lines and refresh bit lines, respectively. When a refresh request and a data access instruction are applied on the same row, it is determined which of refresh and data access is instructed earlier, and one of... | 05/14/2002 |
| 6365520 | Small particle size chemical mechanical polishing composition The present invention provides a chemical mechanical polishing slurry for the planarization of shallow trench isolation structures and other integrated circuit structures. The chemical mechanical polishing slurry of this invention comprises small abrasive... | 04/02/2002 |
| 6350694 | Reducing CMP scratch, dishing and erosion by post CMP etch back method for low-k materials A new plasma etch back is provided that is applied to the surface of a low-k dielectric after the process of CMP of a copper surface has been completed. The copper surface is the surface of interconnect metal, the interconnect metal is embedded in the lay... | 02/26/2002 |
| 6325676 | Gas etchant composition and method for simultaneously etching silicon oxide and polysilicon, and method for manufacturing semiconductor device using the same A gas etchant composition and a method for simultaneously etching-back silicon oxide and polysilicon at substantially similar etching rates are used for manufacturing semiconductor devices. The gas etchant composition to be utilized for dry-etching includ... | 12/04/2001 |
