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| Number | Title | Issue Date |
| 7419909 | Methods of forming a semiconductor device that allow patterns in different regions that have different pitches to be connected Patterns are formed in a semiconductor device by defining a lower layer that includes a first region and a second region on a semiconductor substrate, forming first patterns with a first pitch that extend to the first and second regions, forming second patterns with... | 09/02/2008 |
| 7396737 | Method of forming shallow trench isolation A method of manufacturing a semiconductor device including forming a pad oxide layer on a semiconductor substrate, forming a spacer oxide layer pattern on sidewalls of the pad oxide layer, and forming a nitride layer on the pad oxide layer. The method further includ... | 07/08/2008 |
| 7393789 | Protective coating for planarization Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolida... | 07/01/2008 |
| 7393737 | Semiconductor device and a method of manufacturing the same A semiconductor device which, in spite of the existence of a dummy active region, eliminates the need for a larger chip area and improves the surface flatness of the semiconductor substrate. In the process of manufacturing it, a thick gate insulating film for a high... | 07/01/2008 |
| 7361598 | Method for fabricating semiconductor device capable of preventing scratch Disclosed is a method for fabricating a semiconductor device capable of preventing scratches. The method includes the steps of: forming a substrate divided into a peripheral region and a cell region where a capacitor including a metal plate electrode on which partic... | 04/22/2008 |
| 7358587 | Semiconductor structures In one aspect, the invention includes a method of forming a material within an opening, comprising: a) forming an etch-stop layer over a substrate, the etch-stop layer having an opening extending therethrough to expose a portion of the underlying substrate and compr... | 04/15/2008 |
| 7358196 | Wet chemical treatment to form a thin oxide for high k gate dielectrics Described herein are methods of forming a thin silicon dioxide layer having a thickness of less than eight angstroms on a semiconductor substrate to form the bottom layer of a gate dielectric. A silicon dioxide layer having a thickness of less than eight angstroms m... | 04/15/2008 |
| 7338905 | Semiconductor device manufacture method An electric conductive film is formed on the insulating surface of a substrate, the substrate having a trench formed on the insulating surface, and the conductive film being filled in the trench. Chemical mechanical polishing is executed to expose the insulating sur... | 03/04/2008 |
| 7282434 | Method of manufacturing a semiconductor device A method of manufacturing a semiconductor integrated circuit device is provided including forming a first insulating film comprised of fluorine-containing silicon oxide over a main surface of a semiconductor substrate is formed together with forming a second insulat... | 10/16/2007 |
| 7276426 | Methods of forming semiconductor constructions The invention includes a method of forming a semiconductor construction. A semiconductor substrate is placed within a reaction chamber. The substrate comprises a center region and an edge region surrounding the center region. The substrate comprises openings within ... | 10/02/2007 |
| 7271100 | Slurry composition, polishing method using the slurry composition and method of forming a gate pattern using the slurry composition A slurry composition includes about 4.25 to about 18.5 weight percent of an abrasive, about 80 to about 95 weight percent of deionized water, and about 0.05 to about 1.5 weight percent of an additive. The slurry composition may further include a surfactant. In a pol... | 09/18/2007 |
| 7148103 | Multilevel poly-Si tiling for semiconductor circuit manufacture Method of manufacturing a semiconductor device, including a first baseline technology electronic circuit (1) and a second option technology electronic circuit (2) as functional parts of a system-on-chip, by: manufacturing the first electro... | 12/12/2006 |
| 6703318 | Method of planarizing a semiconductor die A method of CMP planarizing a silicon dioxide layer on a silicon nitride in the semiconductor die is disclosed. A wafer has a plurality substantially identical semiconductor dies defined on the wafer. Each of the dies is separated from one another by a sc... | 03/09/2004 |
| 6703287 | Production method for shallow trench insulation An improved method for producing a semiconductor device in which overpolishing is prevented at a chemical mechanical polishing time to eliminate the influence of peripheries on the object part. A plasma oxide film is formed on a semiconductor substrate so... | 03/09/2004 |
| 6703270 | Method of manufacturing a semiconductor device A method of manufacturing a semiconductor device comprises the steps of: forming a patterned masking layer (3) of insulating material at a surface (2) of a semiconductor body (1), etching the semiconductor body (1) through the patterned masking layer (3) ... | 03/09/2004 |
| 6699791 | Methods and apparatuses for monitoring and controlling mechanical or chemical-mechanical planarization of microelectronic substrate assemblies Methods and devices for mechanical and/or chemical-mechanical planarization of semiconductor wafers, field emission displays and other microelectronic substrate assemblies. One method of planarizing a microelectronic substrate assembly in accordance with ... | 03/02/2004 |
| 6699766 | Method of fabricating an integral capacitor and gate transistor having nitride and oxide polish stop layers using chemical mechanical polishing elimination A system, apparatus and/or method is provided for fabricating an integrated capacitor during the fabrication of a transistor employing chemical mechanical polishing of a gate electrode of the transistor. Components of the integrated capacitor, particularl... | 03/02/2004 |
| 6700143 | Dummy structures that protect circuit elements during polishing Circuit elements (e.g. transistor gates) formed over a semiconductor substrate are protected by adjacent dummy structures during mechanical or chemical mechanical polishing of an overlying dielectric.... | 03/02/2004 |
| 6699725 | Methods of fabricating ferroelectric memory devices having a ferroelectric planarization layer In the present invention, ferroelectric memory devices using a ferroelectric planarization layer and methods of fabricating the same are disclosed. According to the method of the present invention, a conductive layer is formed on an interlayer insulation ... | 03/02/2004 |
| 6699299 | Composition and method for polishing in metal CMP A composition is provided in the present invention for polishing a composite semiconductor structure containing a metal layer (such as tungsten, aluminum, or copper), a barrier layer (such as tantalum, tantalum nitride, titanium, or titanium nitride), and... | 03/02/2004 |
| 6699799 | Method of forming a semiconductor device A method of forming a semiconductor device includes a liner is conformally stacked on a semiconductor substrate before coating an SOG layer thereon, and then curing the SOG layer, preferably in an ambient of oxygen radicals formed at a temperature of 1000... | 03/02/2004 |
| 6696759 | Semiconductor device with diamond-like carbon layer as a polish-stop layer A semiconductor structure includes a diamond-like carbon layer as a polish-stop for patterning a metal level into an inter-level dielectric substrate in a damascene process flow. The semiconductor structure includes a substrate having a dielectric layer f... | 02/24/2004 |
| 6693357 | Methods and semiconductor devices with wiring layer fill structures to improve planarization uniformity Semiconductor devices and manufacturing methods therefor are disclosed, in which conductive fill structures are provided in fill regions in an interconnect wiring layer between conductive wiring structures to facilitate planarization uniformity during met... | 02/17/2004 |
| 6693034 | Deadhesion method and mechanism for wafer processing A method of manufacturing semiconductor devices using an improved planarization process for the planarization of the surfaces of the wafer on which the semiconductor devices are formed. The improved planarization process includes the formation of a flat p... | 02/17/2004 |
| 6693315 | Semiconductor device with an active region and plural dummy regions There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns c... | 02/17/2004 |
| 6693035 | Methods to control film removal rates for improved polishing in metal CMP A method for chemical mechanical planarization of a semiconductor structure comprised of a conductive metal interconnect layer, a barrier or liner film, and an underlying dielectric layer using a two-step polishing process is provided. In the first step, ... | 02/17/2004 |
| 6690045 | Semiconductor device with reduced CMP dishing A semiconductor device comprises a plurality of superposed layers including a predetermined layer provided, in a peripheral part of a chip, with a dummy pattern of a material that is the same as that forming a wiring pattern formed in the same predetermin... | 02/10/2004 |
| 6682617 | Method for making wallboard or backerboard sheets including aerated concrete A method for making wallboard or backerboard sheets which are relatively lightweight, strong, and which have good fire resistance, thermal insulation, and sound absorbing properties includes forming core material having opposing first and second major sur... | 01/27/2004 |
| 6682985 | Semiconductor device and manufacturing method thereof A semiconductor device as well as a method of manufacturing a semiconductor device wherein a wide trench separation band is formed without causing the scooping out of the silicon substrate can be gained. The process is provided with the step of forming a multi... | 01/27/2004 |
| 6669748 | Dispersion liquid of silica particles for polishing, method of producing the same, and polishing agent The present invention provides a dispersion liquid of silica particles for polishing with a low content of Na ions and also with a content of ions other than Na ions in a prespecified range. This dispersion liquid is a dispersion liquid of silica particle... | 12/30/2003 |
| 6664190 | Pre STI-CMP planarization scheme A new method of forming shallow trench isolations using a reverse mask process is described. A polish stop layer is deposited on the surface of a substrate. An etch stop layer is deposited overlying the polish stop layer. A plurality of isolation trenches... | 12/16/2003 |
| 6663468 | Method for polishing surface of semiconductor device substrate The problem of non-uniform polishing properties of a circumferential surface area of a substrate, so-called edge sagging phenomenon, is solved. When a thin film formed on a top surface of the substrate is polished while holding a back surface of the subst... | 12/16/2003 |
| 6660641 | Method for forming crack resistant planarizing layer within microelectronic fabrication Within a method for forming a planarizing layer within a microelectronic fabrication, there is employed formed upon a partially photoexposed planarizing layer formed of a partially photoexposed negative photoresist material a sacrificial layer. Within the... | 12/09/2003 |
| 6653202 | Method of shallow trench isolation (STI) formation using amorphous carbon An exemplary embodiment relates to a method of shallow trench isolation (STI) formation using amorphous carbon as a sacrificial polish stop layer. The method can include polishing a silicon dioxide layer located above a wafer, polishing portions of the si... | 11/25/2003 |
| 6653671 | Semiconductor device A semiconductor device has a dummy pattern including an underlying layer which is formed on a semiconductor substrate and in which a plurality of word lines from N-2 to N+2 are arranged in parallel, a plurality of blocks each of which has a plurality of d... | 11/25/2003 |
| 6653722 | Method for applying uniform pressurized film across wafer A method of manufacturing semiconductor devices using an improved planarization process for the planarization of the surfaces of the wafer on which the semiconductor devices are formed. The improved planarization process includes the formation of a flat p... | 11/25/2003 |
| 6652764 | Methods and apparatuses for making and using planarizing pads for mechanical and chemical-mechanical planarization of microelectronic substrates Methods and apparatuses for planarizing a microelectronic substrate. In one embodiment, a planarizing pad for mechanical or chemical-mechanical planarization includes a base section and a plurality of embedded sections. The base section has a planarizing ... | 11/25/2003 |
| 6652363 | Method and apparatus for uniformly planarizing a microelectronic substrate A method and apparatus for planarizing a microelectronic substrate. The apparatus can include a planarizing medium having a relatively hard polishing pad and a planarizing liquid disposed on a generally non-porous planarizing surface of the polishing pad.... | 11/25/2003 |
| 6653717 | Enhancement in throughput and planarity during CMP using a dielectric stack containing an HDP oxide A semiconductor device and process for making the same are disclosed which use reticulated conductors and a width-selective planarizing interlevel dielectric (ILD) deposition process to improve planarity of an interconnect layer. Reticulated conductor 52 ... | 11/25/2003 |
| 6649523 | Method and system to provide material removal and planarization employing a reactive pad Systems and methods to remove a first material located on a top surface of a workpiece are presented according to one aspect of the present invention. According to an exemplary method, the pad including a second material is positioned proximate to the wor... | 11/18/2003 |
