Class 257/E21.236 - Process specially adapted to improve resolution of mask (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.233. This subclass
No. of patents: 23
Last issue date: 09/04/2007

Number	Title	Issue Date
7265059	Multiple fin formation A FinFET includes a plurality of semiconductor fins. Over a semiconductor layer, patterned features (e.g. of minimum photolithographic size and spacing) are formed. In one example of fin formation, a first set of sidewall spacers are formed adjacent to the sides of ...	09/04/2007
6580150	Vertical junction field effect semiconductor diodes Semiconductor diodes are diode connected vertical cylindrical field effect devices having one diode terminal as the common connection between a gate and a source/drain of the vertical cylindrical field effect devices. Methods of forming the diode connecte...	06/17/2003
6500744	Methods of forming DRAM assemblies, transistor devices, and openings in substrates The invention encompasses a method of forming an opening in a substrate. A first expanse of a first material is formed over the substrate, and such expanse comprises a sidewall edge. A second material is formed along the sidewall edge, and subsequently a ...	12/31/2002
6391782	Process for forming multiple active lines and gate-all-around MOSFET An ultra-large-scale integrated (ULSI) circuit includes MOSFETs. The MOSFETs can include a gate structure above active lines manufactured by utilizing a spacer structure as a mask. The spacer structure can be silicon dioxide formed in an etch back process...	05/21/2002
6358800	Method of forming a MOSFET with a recessed-gate having a channel length beyond photolithography limit A method of forming a MOSFET having a recessed-gate with a channel length beyond the photolithography limit is disclosed in the present invention. First, a first dielectric layer and a second dielectric layer are formed on a semiconductor substrate. A fir...	03/19/2002
6329227	Method of patterning organic polymer film and method for fabricating semiconductor device An organic polymer film patterning method includes the steps of: defining a resist film on a selected area of a substrate; depositing an organic polymer film over the substrate by a plasma CVD process so that the resist film is covered with part of the or...	12/11/2001
6329124	Method to produce high density memory cells and small spaces by using nitride spacer The present invention relates to a method for forming an etch mask. A photoresist layer is patterned, wherein d1 is a smallest space dimension of an exposed area of a layer underlying the photoresist layer. An ARC layer under the photoresist la...	12/11/2001
6228747	Organic sidewall spacers used with resist Disposable spacers of an organic material or a low-temperature inorganic material provide advantages in the formation of STI trenches and contact holes and additional freedom in line spacing....	05/08/2001
6121155	Integrated circuit fabrication critical dimension control using self-limiting resist etch The present invention provides a process for self-limiting trim etch of patterned photoresist that will allow integrated circuit fabrication to achieve smaller integrated circuit component features and greatly reduce final critical dimension drift or vari...	09/19/2000
6030903	Non-destructive method for gauging undercut in a hidden layer A method for non-destructively determining the amount of undercutting in a hidden layer of material disposed on a substrate after device patterning by etching. The method involves forming at least two lines of etch resistant material of increasing width o...	02/29/2000
5935454	Ultrafine fabrication method A method of fabricating nanometric structures on a substrate by dry etching includes setting the substrate at a temperature at which condensation of etching gas products of etching gas decomposed, recombined and reacted, or products of reactions between t...	08/10/1999
5753524	Method of forming a plateau and a cover on the plateau in particular on a semiconductor substrate Prior to using etching to form a plateau that is to constitute a laser ridge and that is to be provided with a cover constituting a top electrode, the surface of the cover is initially protected with a dielectric mask and the flanks of the cover are then ...	05/19/1998
5705321	Method for manufacture of quantum sized periodic structures in Si materials Multiple-exposure fine-line interferometric lithography, combined with conventional optical lithography, is used in a sequence of steps to define arrays of complex, nm-scale structures in a photoresist layer. Nonlinearities in the develop, mask etch, and ...	01/06/1998
5675164	High performance multi-mesa field effect transistor A high performance transistor includes mesa structures in a conduction region, favoring corner conduction, together with lightly doped mesa structures and mid-gap gate material also favoring operation in a fully depleted mode. Mesa structures are formed a...	10/07/1997
5665622	Folded trench and rie/deposition process for high-value capacitors Isotropic deposition of a selectively etchable material in an opening in a body of material followed by isotropic deposition of an etch resistant material forms a mask for anisotropic etching of the selectively etchable material at potentially sub-lithogr...	09/09/1997
5328810	Method for reducing, by a factor or 2^-N, the minimum masking pitch of a photolithographic process The process starts with a primary mask, which may be characterized as a pattern of parallel, photoresist strips having substantially vertical edges, each having a minimum feature width F, and being separated from neighboring strips by a minimum space widt...	07/12/1994
5096848	Method for forming semiconductor device isolating regions A method for forming semiconductor device isolation regions including steps of forming a first insulating film on a semiconductor substrate, removing the first insulating film in a portion to become a device isolation region with use of a resist pattern f...	03/17/1992
4871630	Mask using lithographic image size reduction Disclosed is a process for reducing lithographic image size for integrated circuit manufacture. A mask of photosensitive material having an opening of a minimum size dictated by the limits of lithography is formed on a substrate. Reduction in the image si...	10/03/1989
4735681	Fabrication method for sub-micron trench A method for the construction of self aligned submicron trenches by forming projecting ridges on a surface, forming a mask over the surface and then etching back the ridges to form gaps in the mask which act as guides for the etching of trenches in the su...	04/05/1988
4707218	Lithographic image size reduction Disclosed is a process for reducing lithographic image size for integrated circuit manufacture. A mask of photosensitive material having an opening of a minimum size dictated by the limits of lithography is formed on a substrate. Reduction in the image si...	11/17/1987
4502914	Method of making structures with dimensions in the sub-micrometer range Following the method of making structures with dimensions in the submicrometer range, structures of a polymeric layer with horizontal and substantially vertical surfaces are first made on a substrate. Thereupon, a silicon nitride or oxide layer is plasma ...	03/05/1985
4472240	Method for manufacturing semiconductor device A method for forming a groove in a semiconductor substrate is disclosed. The groove is formed in two steps. In the first step, a first shallow groove is formed in the semiconductor substrate and then a first mask pattern is selectively formed on the wall ...	09/18/1984
4274909	Method for forming ultra fine deep dielectric isolation A method is shown for forming ultra fine, deep dielectric isolation in a silicon body. The method involves forming a first layer of material on the silicon body over a first set of alternately designated device regions. A conformal coating is deposited ov...	06/23/1981

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Class 257/E21.236 - Process specially adapted to improve resolution of mask (EPO)