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| Number | Title | Issue Date |
| 7435654 | Analog capacitor having at least three high-k dielectric layers, and method of fabricating the same There are provided an analog capacitor having at least three high-k dielectric layers, and a method of fabricating the same. The analog capacitor includes a lower electrode, an upper electrode, and at least three high-k dielectric layers interposed between the lower... | 10/14/2008 |
| 7396748 | Semiconductor device includes gate insulating film having a high dielectric constant A semiconductor device comprising a semiconductor substrate and a MOSFET provided on the semiconductor substrate, the MOSFET including a gate insulating film and a gate electrode provided on the gate insulating film, wherein the gate insulating film has a higher die... | 07/08/2008 |
| 7361559 | Manufacturing method for a MOS transistor comprising layered relaxed and strained SiGe layers as a channel region The invention includes non-volatile memory and logic devices associated with crystalline Si/Ge. The devices can include TFT constructions. The non-volatile devices include a floating gate or floating plate over the Si/Ge, and a pair of source/drain regions. The sour... | 04/22/2008 |
| 7288802 | Virtual body-contacted trigate A field effect transistor (FET) and method of forming the FET comprises a substrate; a silicon germanium (SiGe) layer over the substrate; a semiconductor layer over and adjacent to the SiGe layer; an insulating layer adjacent to the substrate, the SiGe layer, and th... | 10/30/2007 |
| 7253061 | Method of forming a gate insulator in group III-V nitride semiconductor devices A method of forming a gate insulator in the manufacture of a semiconductor device comprises conducting a photo-assisted electrochemical process to form a gate-insulating layer on a gallium nitride layer of the semiconductor device, wherein the gate-insulating layer ... | 08/07/2007 |
| 7247896 | Semiconductor devices having a field effect transistor and methods of fabricating the same A semiconductor device having a field effect transistor and a method of forming the same are provided. The semiconductor device preferably includes a device active pattern disposed on a predetermined region of the substrate. The gate electrode preferably crosses ove... | 07/24/2007 |
| 7202122 | Cobalt silicidation process for substrates with a silicon—germanium layer A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a... | 04/10/2007 |
| 7176504 | SiGe MOSFET with an erosion preventing SiGelayer A semiconductor device is provided. The semiconductor device comprises a substrate, a gate structure, a spacer, a SixGey layer and a SixGey protection layer. The gate structure is deposited on the substrate and the spacer ... | 02/13/2007 |
| 7166897 | Method and apparatus for performance enhancement in an asymmetrical semiconductor device A method and apparatus is presented that provides performance enhancement in a semiconductor device. In one embodiment, a first current region (64, 76, 23), a channel region and a second current region (75, 33, 66) are adjacent each other. The second c... | 01/23/2007 |
| 7118973 | Method of forming a transistor with a channel region in a layer of composite material The vertical diffusion of dopants from the gate and the bulk material into the channel region, and the lateral diffusion of dopants from the source and drain regions into the channel region resulting from thermal cycling during the fabrication of a MOS transistor is... | 10/10/2006 |
| 6949761 | Structure for and method of fabricating a high-mobility field-effect transistor A structure and method of fabricating a high-mobility semiconductor layer structure and field-effect transistor (MODFET) that includes a high-mobility conducting channel, while at the same time, maintaining counter doping to control deleterious short-channel effects... | 09/27/2005 |
| 6703291 | Selective NiGe wet etch for transistors with Ge body and/or Ge source/drain extensions The wet etch stage of the salicide process normally used to fabricate polysilicon and silicon-based semiconductor transistors may not be appropriate for germanium-based transistors because the wet etch chemicals at such temperatures will dissolve the germ... | 03/09/2004 |
| 6635110 | Cyclic thermal anneal for dislocation reduction The invention provides processes for producing a very low dislocation density in heterogeneous epitaxial layers with a wide range of thicknesses, including a thickness compatible with conventional silicon CMOS processing. In a process for reducing disloca... | 10/21/2003 |
| 6486520 | Structure and method for a large-permittivity gate using a germanium layer A structure for, and method of forming, a metal-insulator-semiconductor field-effect transistor in an integrated circuit is disclosed. The disclosed method comprises forming a germanium layer 52 on a semiconductor substrate (e.g. silicon 20), depositing a... | 11/26/2002 |
| 6352942 | Oxidation of silicon on germanium The invention provides processes for producing a high-quality silicon dioxide layer on a germanium layer. In one example process, a layer of silicon is deposited on the germanium layer, and the silicon layer is exposed to dry oxygen gas at a temperature t... | 03/05/2002 |
| 6350311 | Method for forming an epitaxial silicon-germanium layer A method for growing an epitaxial silicon-germanium layer is described. The method includes removing a native oxide layer on the silicon substrate surface. A HF vapor treatment process is then conducted on the silicon substrate. Thereafter, a germanium la... | 02/26/2002 |
| 6287903 | Structure and method for a large-permittivity dielectric using a germanium layer A structure for, and method of forming, a metal-insulator-semiconductor field-effect transistor in an integrated circuit is disclosed. The disclosed method comprises forming a germanium layer 52 on a semiconductor substrate (e.g. silicon 20), depositing a... | 09/11/2001 |
| 6235560 | Silicon-germanium transistor and associated methods A method for making a transistor includes the steps of providing a silicon substrate including a silicon-germanium epitaxial layer, forming a masking implant layer on a channel region of the silicon-germanium epitaxial layer, and implanting dopants into t... | 05/22/2001 |
| 5798555 | Enhancement-depletion logic based on Ge mosfets The present invention discloses a method of forming an oxide layer on a layer of germanium including the steps of depositing a layer of aluminum arsenide on the layer of germanium, of exposing the layer of aluminum arsenide to an oxidizing gas mixture so ... | 08/25/1998 |
| 5780922 | Ultra-low phase noise GE MOSFETs A germanium-based field effect transistor has a passivation layer of aluminum oxide below a germanium channel and aluminum oxide gate oxide layer formed over the channel. The aluminum oxide layers are treated to reduce the density of surface state impurit... | 07/14/1998 |
| 5705412 | Method of making buried gate insulator field effect transistor A buried, gate insulator field effect transistor is disclosed. It comprises source, drain, substrate, gate, and a gate insulator layer separating the gate from the source, drain and substrate; and a protective silicon dioxide covering layer. Windows are e... | 01/06/1998 |
| 5602403 | Ion Implantation buried gate insulator field effect transistor A buried, gate insulator field effect transistor is disclosed. It comprises a source, drain, substrate, gate, and a gate insulator layer separating the gate from the source, drain and substrate; and a protective silicon dioxide covering layer. Windows are... | 02/11/1997 |
