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| Number | Title | Issue Date |
| 7432559 | Silicide formation on SiGe A semiconductor structure includes a first silicon-containing layer comprising an element selected from the group consisting essentially of carbon and germanium wherein the silicon-containing layer has a first atomic percentage of the element to the element and sili... | 10/07/2008 |
| 7394103 | All diamond self-aligned thin film transistor A substantially all diamond transistor with an electrically insulating substrate, an electrically conductive diamond layer on the substrate, and a source and a drain contact on the electrically conductive diamond layer. An electrically insulating diamond layer is in... | 07/01/2008 |
| 7391078 | Non-volatile memory and manufacturing and operating method thereof A non-volatile memory is provided. A substrate having a plurality of trenches and a plurality of select gates is provided. The trenches are arranged in parallel and extend in a first direction. Each of the select gates is disposed on the substrate between two adjace... | 06/24/2008 |
| 7366026 | Flash memory device and method for fabricating the same, and programming and erasing method thereof A flash memory device of SONOS structure and a method for fabricating the same, and programming and erasing operation methods, to improve reliability such as endurance and retention, are disclosed, which includes a first conductive type semiconductor substrate; an O... | 04/29/2008 |
| 7364989 | Strain control of epitaxial oxide films using virtual substrates A method of controlling strain in a single-crystal, epitaxial oxide film, includes preparing a silicon substrate; forming a silicon alloy layer taken from the group of silicon alloy layer consisting of Si1-xGex and Si1-yCy | 04/29/2008 |
| 7361559 | Manufacturing method for a MOS transistor comprising layered relaxed and strained SiGe layers as a channel region The invention includes non-volatile memory and logic devices associated with crystalline Si/Ge. The devices can include TFT constructions. The non-volatile devices include a floating gate or floating plate over the Si/Ge, and a pair of source/drain regions. The sour... | 04/22/2008 |
| 7329606 | Semiconductor device having nanowire contact structures and method for its fabrication A semiconductor device having small electrical contacts to impurity doped regions and a method for fabrication of such a device are provided. In accordance with one embodiment of the invention the semiconductor device comprises a semiconductor substrate having a dop... | 02/12/2008 |
| 7312136 | Method of fabricating a wafer with strained channel layers for increased electron and hole mobility for improving device performance A method for making a SOI wafer with a strained silicon layer for increased electron and hole mobility is achieved. The method forms a porous silicon layer on a seed wafer. A H2 anneal is used to form a smooth surface on the porous silicon. A strain free ... | 12/25/2007 |
| 7274055 | Method for improving transistor performance through reducing the salicide interface resistance An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the sour... | 09/25/2007 |
| 7265420 | Semiconductor substrate layer configured for inducement of compressive or expansive force An integrated circuit (IC) utilizes a strained layer. The substrate can utilize trenches in a base layer to induce stress in a layer. The trenches define pillars on a back side of a bulk substrate or base layer of a semiconductor-on-insulator (SOI) wafer. ... | 09/04/2007 |
| 7238985 | Trench type mosgated device with strained layer on trench sidewall A MOSgated trench device has a reduced on resistance by forming a less than about a 13 nm thick strained SiGe layer on the silicon surface of the trenches and forming a thin (30 nm or less) layer of epitaxially deposited silicon on the SiGe layer which epi layer is ... | 07/03/2007 |
| 7223679 | Transistor gate electrode having conductor material layer Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor mate... | 05/29/2007 |
| 7166897 | Method and apparatus for performance enhancement in an asymmetrical semiconductor device A method and apparatus is presented that provides performance enhancement in a semiconductor device. In one embodiment, a first current region (64, 76, 23), a channel region and a second current region (75, 33, 66) are adjacent each other. The second c... | 01/23/2007 |
| 7125786 | Method of forming vias in silicon carbide and resulting devices and circuits A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding that can otherwise cause undesired inductance. The method includes fabricating a semiconductor device in epitaxial layers on a surface of a silicon... | 10/24/2006 |
| 7118973 | Method of forming a transistor with a channel region in a layer of composite material The vertical diffusion of dopants from the gate and the bulk material into the channel region, and the lateral diffusion of dopants from the source and drain regions into the channel region resulting from thermal cycling during the fabrication of a MOS transistor is... | 10/10/2006 |
| 6949761 | Structure for and method of fabricating a high-mobility field-effect transistor A structure and method of fabricating a high-mobility semiconductor layer structure and field-effect transistor (MODFET) that includes a high-mobility conducting channel, while at the same time, maintaining counter doping to control deleterious short-channel effects... | 09/27/2005 |
| 6878580 | Semiconductor device having gate with negative slope and method for manufacturing the same A semiconductor device having a gate with a negative slope and a method of manufacturing the same. A poly-SiGe layer with a Ge density profile which decreases linearly from the bottom of the gate toward the top of the gate is formed and a poly-SiGe gate having a neg... | 04/12/2005 |
