Class 257/E21.178 - Joint-gate structure (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.177. This subclass
No. of patents: 4
Last issue date: 07/29/2008

Number	Title	Issue Date
7405110	Methods of forming implant regions relative to transistor gates The invention includes methods of forming implant regions between and/or under transistor gates. In one aspect, a pair of transistor gates is partially formed, and a layer of conductive material is left extending between the transistor gates. A dopant is implanted t...	07/29/2008
7223641	Semiconductor device, method for manufacturing the same, liquid crystal television and EL television A method for manufacturing a semiconductor device by a small number of processes and by a means with high usability of materials to have high-definition and a gate insulating with a high step coverage property is disclosed. According to the present invention, a meth...	05/29/2007
7160780	Method of manufacturing a fin field effect transistor In an exemplary embodiment, a fin active region is protruded along one direction from a bulk silicon substrate on which a shallow trench insulator is entirely formed so as to cover the fin active region. The shallow trench insulator is removed to selectively expose ...	01/09/2007
7144779	Method of forming epitaxial silicon-comprising material The invention includes methods of forming epitaxial silicon-comprising material and methods of forming vertical transistors. In one implementation, a method of forming epitaxial silicon-comprising material includes providing a substrate comprising monocrystalline ma...	12/05/2006

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