Did You Know...
...that after Parker Brothers executives turned down the game of Monopoly because it had "52 fundamental errors" (including taking too long to play), a copy of the game wound up in the home of the company president who stayed up until 1 a.m. to finish playing it? He was so impressed by the game that the next day he wrote to inventor Charles Darrow and offered to buy it!
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| Number | Title | Issue Date |
| 7442632 | Semiconductor device n-channel type MOS transistor with gate electrode layer featuring small average polycrystalline silicon grain size In a semiconductor device including a semiconductor substrate, and an n-channel type MOS transistor produced in the semiconductor substrate, the n-channel type MOS transistor includes a gate insulating layer formed on the semiconductor substrate and having a thickne... | 10/28/2008 |
| 7439105 | Metal gate with zirconium A gate electrode (202) for a transistor including a metal gate structure (207) containing zirconium and a polycrystalline silicon cap (209) located there over. The metal gate structure (207) is located over a gate dielectric (205).... | 10/21/2008 |
| 7427541 | Carbon nanotube energy well (CNEW) field effect transistor A structure to form an energy well within a Carbon nanotube is described. The structure includes a doped semiconductor region and an undoped semiconductor region. The Carbon nanotube is between the doped semiconductor region and the undoped semiconductor region. The... | 09/23/2008 |
| 7407846 | Thin film transistor, display device and their production The present method prevents malfunctions in switching caused by a light leakage current in an active matrix type thin film transistor substrate for a liquid crystal display and prevents display failures, by selectively disposing a self assembled monolayer film in a ... | 08/05/2008 |
| 7394135 | Dual source MOSFET for low inductance synchronous rectifier A dual source MOSFET comprises a large number of cells diffused into a substrate. The cells are divided into two regions with separate sources and gates but having a common drain connection, the substrate. It is preferred that the source regions be highly interdigit... | 07/01/2008 |
| 7374984 | Method of forming a thin film component Embodiments of methods, apparatuses, devices, and/or systems for forming a thin film component are described. ... | 05/20/2008 |
| 7361580 | Semiconductor device and manufacturing method thereof A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a gate insulating layer, a gate electrode, an oxide layer, and sidewalls. The gate insulating layer is formed on the substrate. The gate electrode ... | 04/22/2008 |
| 7323392 | High performance transistor with a highly stressed channel A MOS transistor having a highly stressed channel region and a method for forming the same are provided. The method includes forming a first semiconductor plate over a semiconductor substrate, forming a second semiconductor plate on the first semiconductor plate whe... | 01/29/2008 |
| 7285451 | Semiconductor integrated circuit device manufacturing method To reduce variation in channel lengths of MOS transistors within a circuit functional module. When exposure of a wafer substrate having a semiconductor integrated circuit device 1 including a plurality of CMOS circuit module regions CCM11 to CCM22 | 10/23/2007 |
| 7268029 | Method of fabricating CMOS transistor that prevents gate thinning Provided is a method of fabricating a CMOS transistor in which, after a polysilicon layer used as a gate is formed on a semiconductor substrate, a photoresist pattern that exposes an n-MOS transistor region is formed on the polysilicon layer. An impurity is implante... | 09/11/2007 |
| 7202148 | Method utilizing compensation features in semiconductor processing A photolithography and etch process sequence includes a photomask having a pattern with compensation features that alleviate patterning variations due to the proximity effect and depth of focus concerns during photolithography. The compensation features may be dispo... | 04/10/2007 |
| 7183185 | Methods of forming transistor gates; and methods of forming programmable read-only memory constructions The invention includes a method of forming a transistor gate. One or more conductive materials are formed over a semiconductor substrate, and a block is formed over the one or more conductive materials. The block comprises a photoresist mass and a material other tha... | 02/27/2007 |
| 7179709 | Method of fabricating non-volatile memory device having local SONOS gate structure in methods of fabricating a non-volatile memory device having a local silicon-oxide-nitride-oxide-silicon (SONOS) gate structure, a semiconductor substrate having a cell transistor area, a high voltage transistor area, and a low voltage transistor area, is prepared.... | 02/20/2007 |
| 7144784 | Method of forming a semiconductor device and structure thereof In one embodiment, a method for forming a semiconductor device is described. A semiconductor substrate has a first portion and a second portion. A first dielectric layer formed over the first portion of the semiconductor substrate and a second dielectric layer is fo... | 12/05/2006 |
| 7144773 | Method for preventing trenching in fabricating split gate flash devices A method for forming a split gate flash device is provided. In one embodiment, a semiconductor substrate with a dielectric layer formed thereover is provided. A conductor layer is formed overlying the dielectric layer. A masking layer is deposited overlying the cond... | 12/05/2006 |
| 7087508 | Method of improving short channel effect and gate oxide reliability by nitrogen plasma treatment before spacer deposition A new method is provided for manufacturing a gate electrode. A layer of gate material, such as polysilicon, is deposited, patterned and etched, defining the poly gate electrode structure. LDD and pocket impurity implants are performed, the LDD profile is created by ... | 08/08/2006 |
| 7078347 | Method for forming MOS transistors with improved sidewall structures A gate structure (30) is formed over a semiconductor (10). Sidewall structures (200) of a first width W1 are formed adjacent to the gate structure (30) and source and drain regions (90) are formed in the semiconductor ( | 07/18/2006 |
| 5661046 | Method of fabricating BiCMOS device A BiCMOS method and device. The BiCMOS device achieves improved performance through the use of wrap-around silicide contacts, improved MOS gate formation, the use of n- and p-type LDD's, the formation of very shallow base regions in bipolar transistors, a... | 08/26/1997 |
| 5258645 | Semiconductor device having MOS transistor and a sidewall with a double insulator layer structure A semiconductor device including a semiconductor substrate with a P-type well formed in the semiconductor substrate and a gate insulator layer formed on the semiconductor substrate. N-type diffusion regions are formed in the P-type well on both sides of t... | 11/02/1993 |
