Did You Know...
...that after Parker Brothers executives turned down the game of Monopoly because it had "52 fundamental errors" (including taking too long to play), a copy of the game wound up in the home of the company president who stayed up until 1 a.m. to finish playing it? He was so impressed by the game that the next day he wrote to inventor Charles Darrow and offered to buy it!
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| Number | Title | Issue Date |
| 7442640 | Semiconductor device manufacturing methods Methods of manufacturing a semiconductor device including a high-voltage device region and a low-voltage device region are provided. An illustrated method includes forming, on a substrate, a gate pattern for a high-voltage device and a low-voltage device; implanting... | 10/28/2008 |
| 7442625 | Apparatus for annealing, method for annealing, and method for manufacturing a semiconductor device An apparatus for annealing a substrate includes a substrate stage having a substrate mounting portion configured to mount the substrate; a heat source having a plurality of heaters disposed under the substrate mounting portion, the heaters individually preheating a ... | 10/28/2008 |
| 7439185 | Method for fabricating semiconductor device and semiconductor device A method of fabricating a semiconductor device having an air-gapped multilayer interconnect wiring structure is disclosed. After having formed a first thin film on or above a substrate, define a first opening in the first thin film. Then, deposit a conductive materi... | 10/21/2008 |
| 7439117 | Method for designing a micro electromechanical device with reduced self-actuation A method is described for designing a micro electromechanical device in which the risk of self-actuation of the device in use is reduced. The method includes locating a first conductor in a plane and locating a second conductor with its collapsible portion at a pred... | 10/21/2008 |
| 7439118 | Method of manufacturing semiconductor integrated circuit A method of manufacturing a semiconductor integrated circuit including a logic part and a memory array part, the logic part having N-type and P-type FETs, and the memory array part having N-type and P-type FETs, includes the steps of forming N-type and P-type FETs c... | 10/21/2008 |
| 7435691 | Micromechanical component and suitable method for its manufacture A micromechanical component having a silicon substrate; a cavity provided in the substrate; and a diaphragm, provided on the surface of the substrate, which closes the cavity; the diaphragm featuring a silicon-oxide layer having an opening that is formed by silicon-... | 10/14/2008 |
| 7435675 | Method of providing a pre-patterned high-k dielectric film A method of forming a pre-patterned high-k dielectric film onto a support layer. The method includes: providing a support layer; providing a template defining template openings therein exhibiting a pattern that is a mirror image of a pattern of the pre-patterned hig... | 10/14/2008 |
| 7436040 | Method and apparatus for diverting void diffusion in integrated circuit conductors A method of diverting void diffusion in an integrated circuit includes steps of forming an electrical conductor having a boundary in a first electrically conductive layer of an integrated circuit, forming a via inside the boundary of the electrical conductor in a di... | 10/14/2008 |
| 7435674 | Dielectric interconnect structures and methods for forming the same Dielectric interconnect structures and methods for forming the same are provided. Specifically, the present invention provides a dielectric interconnect structure having a noble metal layer (e.g., Ru, Ir, Rh, Pt, RuTa, and alloys of Ru, Ir, Rh, Pt, and RuTa) that is... | 10/14/2008 |
| 7432137 | Method of manufacturing thin film transistor A method of manufacturing a thin film transistor includes forming a gate electrode on a substrate; forming a gate insulating film on the gate electrode; forming a semiconductor layer on the gate insulating film; forming a bank including a first bank portion and a se... | 10/07/2008 |
| 7432217 | Method of achieving uniform length of carbon nanotubes (CNTS) and method of manufacturing field emission device (FED) using such CNTS In a method of achieving uniform lengths of Carbon NanoTubes (CNTs) and a method of manufacturing a Field Emission Device (FED) using such CNTs, an organic film is coated to cover CNTs formed on a predetermined material layer. The organic film is etched to a predete... | 10/07/2008 |
| 7432208 | Method of manufacturing suspension structure A method of manufacturing a suspension structure including providing a substrate, forming a first photoresist pattern on the substrate, heating the first photoresist pattern to harden it as a sacrificial layer, forming a second photoresist pattern on the substrate a... | 10/07/2008 |
| 7432200 | Filling narrow and high aspect ratio openings using electroless deposition Methods of fabricating an interconnect utilizing an electroless deposition technique, which fundamentally consists of providing a dielectric material layer having an opening extending into the dielectric material from a first surface thereof, and electrolessly depos... | 10/07/2008 |
| 7432195 | Method for integrating a conformal ruthenium layer into copper metallization of high aspect ratio features A method of integrated processing of a patterned substrate for copper metallization. The method includes providing the patterned substrate containing a via and a trench in a vacuum processing tool, and performing an integrated process on the patterned substrate in t... | 10/07/2008 |
| 7427559 | Method of reducing the surface roughness of spin coated polymer films According to one aspect of the invention, a method of constructing a memory array is provided. An insulating layer is formed on a semiconductor wafer. A first metal stack is then formed on the insulating layer and etched to form first metal lines. A polymeric layer ... | 09/23/2008 |
| 7427807 | Chip heat dissipation structure and manufacturing method This invention discloses a manufacturing method and a structure for a chip heat dissipation. This heat dissipation structure includes a bottom plate of circuit structure, a die of central processing unit and a cap. The cover is often used in conducting the waste hea... | 09/23/2008 |
| 7422943 | Semiconductor device capacitors with oxide-nitride layers and methods of fabricating such capacitors Capacitors having upper electrodes that include a lower electrode, a dielectric layer and an upper electrode that includes a conductive metal nitride layer and a doped polysilicon germanium layer are provided. At least part of the conductive metal nitride layer is o... | 09/09/2008 |
| 7419904 | Method for forming barrier film and method for forming electrode film In the present invention, a barrier film 20 is formed by forming a tungsten nitride film 21 and subsequently by forming a tungsten silicide film 22. The tungsten silicide film 22 is exposed at the surface of the barrier film 20, an... | 09/02/2008 |
| 7419906 | Method for manufacturing a through conductor A method of manufacturing a through conductor that penetrates from an upper surface of a silicon substrate to its lower surface. The through conductor is manufactured in steps which provide a first conductor which extends in the direction of thickness of the silicon... | 09/02/2008 |
| 7416986 | Test structure and method for detecting via contact shorting in shallow trench isolation regions A test structure for detecting void formation in semiconductor device layers includes a plurality of active device areas formed in a substrate, a plurality of shallow trench isolation (STI) regions separating the active device areas, a plurality of gate electrode st... | 08/26/2008 |
| 7416987 | Semiconductor device and method of fabricating the same According to the present invention, there is a provided a semiconductor device fabrication method having, forming a mask material in a surface portion of a semiconductor substrate, and forming a step having a projection by using the mask material; forming a dielectr... | 08/26/2008 |
| 7416978 | Film forming method, film forming system and recording medium After silicon nitride films have been formed on wafers by a film forming process in a reaction vessel, the reaction vessel is processed by a purging process specified by a purging recipe and compatible with the film forming process to suppress production of gases an... | 08/26/2008 |
| 7416908 | Method for fabricating a micro structure A method for fabricating a micro structure includes depositing a first layer of a first material over a substrate; patterning a first hard mask over the first layer; depositing a second layer of a second material over the first layer and the first hard mask; pattern... | 08/26/2008 |
| 7410854 | Method of making FUSI gate and resulting structure Generally disclosed is a method of a device comprising forming a polysilicon stack including a first and a second polysilicon layer with an intervening etch stop layer, wherein the first polysilicon layer height is at least one third a height of the polysilicon stac... | 08/12/2008 |
| 7411244 | Low power electrically alterable nonvolatile memory cells and arrays Nonvolatile memory cells having a conductor-filter system, a conductor-insulator system, and a charge-injection system are provided. The conductor-filter system provides band-pass filtering function, charge-filtering function, and mass-filtering function to charge-c... | 08/12/2008 |
| 7407876 | Method of plasma enhanced atomic layer deposition of TaC and TaCN films having good adhesion to copper A method for processing a substrate for forming TaC and TaCN films having good adhesion to Cu. The method includes disposing the substrate in a process chamber of a plasma enhanced atomic layer deposition (PEALD) system configured to perform a PEALD process, and dep... | 08/05/2008 |
| 7405482 | High-k dielectric film, method of forming the same and related semiconductor device A high-k dielectric film, a method of forming the high-k dielectric film, and a method of forming a related semiconductor device are provided. The high-k dielectric film includes a bottom layer of metal-silicon-oxynitride having a first nitrogen content and a first ... | 07/29/2008 |
| 7396755 | Process and integration scheme for a high sidewall coverage ultra-thin metal seed layer The present invention provides a method of forming a metal seed layer 100. The method includes physical vapor deposition of seed metal 200 within an opening 140 located in a dielectric layer 135 of a substrate 110. The method also ... | 07/08/2008 |
| 7397075 | Method and apparatus providing CMOS imager device pixel with transistor having lower threshold voltage than other imager device transistors A transistor of a pixel cell for use in a CMOS imager with a low threshold voltage of about 0.3 V to less than about 0.7 V is disclosed. The transistor is provided with high dosage source and drain regions around the gate electrode and with the halo implanted region... | 07/08/2008 |
| 7393736 | Atomic layer deposition of ZrHfSnOfilms as high k gate dielectrics The use of atomic layer deposition (ALD) to form a nanolaminate dielectric of zirconium oxide (ZrO2), hafnium oxide (HfO2) and tin oxide (SnO2) acting as a single dielectric layer with a formula of ZrXHfYSn... | 07/01/2008 |
| 7393784 | Method of manufacturing suspension structure and chamber A method of manufacturing a suspension structure including providing a substrate, forming a hole and a sacrificial layer filling the hole on the substrate, forming a patterned photoresist layer on the substrate and the sacrificial layer, the patterned photoresist la... | 07/01/2008 |
| 7384834 | Semiconductor device and a method of manufacturing the same A semiconductor device and a method of manufacturing such a semiconductor device having a field effect transistor with improved current driving performance (e.g., an increase of drain current) of the field effect transistor comprising the steps of ion implanting an ... | 06/10/2008 |
| 7384833 | Stress liner for integrated circuits In one embodiment, a self-aligned contact (SAC) trench structure is formed through a dielectric layer to expose an active region of a MOS transistor. The SAC trench structure not only exposes the active region for electrical connection but also removes portions of a... | 06/10/2008 |
| 7378341 | Automatic process control of after-etch-inspection critical dimension Automatic process control of after-etch-inspection critical dimension. A dielectric layer is deposited over a substrate and is then planarized to a first thickness. A cap oxide layer having a second thickness is deposited, wherein the combination of the first thickn... | 05/27/2008 |
| 7378692 | Integrated electronic circuit comprising superposed components An integrated electronic circuit with at least at least one passive electronic component and at least one active electronic component. The passive electronic component is formed within an insulating material disposed on a substrate. The active component is formed wi... | 05/27/2008 |
| 7378744 | Plasma treatment at film layer to reduce sheet resistance and to improve via contact resistance A method of manufacturing a semiconductor device contact including forming an insulating layer over a substrate and forming an agglutinating layer over the insulating layer. The agglutinating layer is then exposed to a plasma treatment. A barrier layer is formed ove... | 05/27/2008 |
| 7374964 | Atomic layer deposition of CeO/AlOfilms as gate dielectrics The use of atomic layer deposition (ALD) to form a nanolaminate layered dielectric layer of cerium oxide and aluminum oxide acting as a single dielectric layer with a ratio of approximately two to one between the cerium oxide and the aluminum oxide, and a method of ... | 05/20/2008 |
| 7368359 | Method for manufacturing semiconductor substrate and semiconductor substrate A semiconductor substrate (100) is acquired by forming a mask with a target thickness on a major surface of a single-crystal silicon substrate, implanting oxygen ions to the major surface at a high temperature, forming a surface protection layer for blocking ... | 05/06/2008 |
| 7368381 | Methods of forming materials The invention includes methods of forming films over substrates. A substrate is provided within a reaction chamber, and a mixture is also provided within the chamber. The mixture includes a precursor of a desired material within a supercritical fluid. The precursor ... | 05/06/2008 |
| 7368823 | Semiconductor device and method of manufacturing the same A method of manufacturing a semiconductor device having an interconnection part formed of multiple carbon nanotubes is disclosed. The method includes the steps of (a) forming a growth mode control layer controlling the growth mode of the carbon nanotubes, (b) formin... | 05/06/2008 |
