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| Number | Title | Issue Date |
| 7435628 | Method of forming a vertical MOS transistor A vertical MOS transistor has a source region, a channel region, and a drain region that are vertically stacked, and a trench that extends from the top surface of the drain region through the drain region, the channel region, and partially into the source region. Th... | 10/14/2008 |
| 7303967 | Method for fabricating transistor of semiconductor device Disclosed is a method for fabricating a transistor of a semiconductor device, the method comprising the steps of: providing a semiconductor; forming a gate electrode; performing a low-density ion implantation process with respect to the substrate, thereby forming an... | 12/04/2007 |
| 7205588 | Metal fuse for semiconductor devices A method of forming a metal fuse comprising the following steps. A structure is provided having exposed adjacent metal structures. A patterned dielectric layer is formed over the structure. The patterned dielectric layer having via openings 2 exposing at least a por... | 04/17/2007 |
| 7189620 | Semiconductor device including a channel stop structure and method of manufacturing the same It is an object to obtain a semiconductor device comprising a channel stop structure which is excellent in an effect of stabilizing a breakdown voltage and a method of manufacturing the semiconductor device. A silicon oxide film (2) is formed on an upper surf... | 03/13/2007 |
| 7087503 | Shallow self isolated doped implanted silicon process A process and structure for forming electrical devices. The process and structure provide for forming an insulating layer on a substrate. A conductive region is then formed in the insulating layer by implanting silicon atoms into the insulating layer. Further, a plu... | 08/08/2006 |
| 6849529 | Deep-trench capacitor with hemispherical grain silicon surface and method for making the same A method for manufacturing a trench capacitor that includes providing a semiconductor substrate, forming a deep trench in the substrate, forming a thin sacrificial layer on a surface of the trench, and forming a hemispherical silicon grain layer over the thin sacrif... | 02/01/2005 |
| 6700175 | Vertical semiconductor device having alternating conductivity semiconductor regions There is provided a method of manufacturing a vertical semiconductor device including a structural section in which an n- -type semiconductor region and a p- -type semiconductor region are arranged alternately without filling trenche... | 03/02/2004 |
| 6660571 | High voltage power MOSFET having low on-resistance A power MOSFET is provided that includes a substrate of a first conductivity type. An epitaxial layer also of the first conductivity type is deposited on the substrate. First and second body regions are located in the epitaxial layer and define a drift re... | 12/09/2003 |
| 6649308 | Ultra-short channel NMOSFETS with self-aligned silicide contact The ultra-short channel transistor in a semiconductor substrate includes a gate structure that is formed on the substrate. Side-wall spacers are formed on the side walls of the gate structure as an impurities-diffusive source. Source and drain regions are... | 11/18/2003 |
| 6642560 | MOSFET with a thin gate insulating film A semiconductor device comprises: a p-type semiconductor substrate (1); an insulating film (3); a gate electrode (2) formed on the substrata via the insulating film; and an n-type source/drain region (5) formed on both sides of a channel forming region (4... | 11/04/2003 |
| 6642591 | Field-effect transistor A field-effect transistor includes a silicon substrate on which is formed a channel region, a source region and a drain region. A gate insulation layer of a transition metal oxide having a perovskite structure is formed over at least the channel region, a... | 11/04/2003 |
| 6627949 | High voltage power MOSFET having low on-resistance A power MOSFET is provided that includes a substrate of a first conductivity type. An epitaxial layer also of the first conductivity type is deposited on the substrate. First and second body regions are located in the epitaxial layer and define a drift re... | 09/30/2003 |
| 6620668 | Method of fabricating MOS transistor having shallow source/drain junction regions A method of fabricating a MOS transistor having shallow source/drain junction regions is provided. A diffusion source layer is formed on a semiconductor substrate on which gate patterns are formed. Same type or different type of impurities are implanted i... | 09/16/2003 |
| 6617647 | Insulated gate semiconductor device and method of manufacturing the same Dot-pattern-like impurity regions 104 are artificially and locally formed on a channel forming region 103. The impurity regions 104 restrain the expansion of a drain side depletion layer toward the channel forming region 103 to prevent the short channel e... | 09/09/2003 |
| 6610141 | Zinc oxide films containing p-type dopant and process for preparing same A p-type oxide film and a process for preparing the film and p-n or n-p junctions is disclosed. In a preferred embodiment, a p-type zinc oxide film contains arsenic and is grown on a gallium arsenide substrate. The p-type oxide film has a net acceptor con... | 08/26/2003 |
| 6531379 | High resolution dopant/impurity incorporation in semiconductors via a scanned atomic force probe The present invention employs a scanned atomic force probe to physical incorporate impurity atoms (dopant or bandgap) into a semiconductor substrate so that the impurity atoms have high resolution and improved placement. Specifically, the method of the pr... | 03/11/2003 |
| 6506653 | Method using disposable and permanent films for diffusion and implant doping Methods are provided that use disposable and permanent films to dope underlying layers through diffusion. Additionally, methods are provided that use disposable films during implantation doping and that provide a surface from which to dope underlying mate... | 01/14/2003 |
| 6479837 | Thin film transistor and liquid crystal display unit A bottom-gate type thin-film transistor free from alignment shift of the gate electrode and from damage caused by injection of impurities. The crystal grains of a polycrystalline silicon thin-film are anisotropically grown to form a prescribed angle relat... | 11/12/2002 |
| 6475825 | Process for preparing zinc oxide films containing p-type dopant A p-type zinc oxide film and a process for preparing the film is disclosed. In a preferred embodiment, the p-type zinc oxide film contains arsenic and is grown on a gallium arsenide substrate. The p-type zinc oxide film has a net acceptor concentration of... | 11/05/2002 |
| 6455380 | Semiconductor device and method for fabricating the same A semiconductor device is disclosed, including: a semiconductor substrate; a gate electrode formed on the semiconductor substrate; a first gate insulating layer formed between the gate electrode and semiconductor substrate, and formed at a first region in... | 09/24/2002 |
| 6410162 | Zinc oxide films containing P-type dopant and process for preparing same A p-type zinc oxide film and a process for preparing the film and p-n or n-p junctions is disclosed. In a preferred embodiment, the p-type zinc oxide film contains arsenic and is grown on a gallium arsenide substrate. The p-type zinc oxide film has a net ... | 06/25/2002 |
| 6410410 | Method of forming lightly doped regions in a semiconductor device A method is disclosed in which a lightly doped region in a semiconductor layer is obtained by diffusing dopant atoms of a first and second type into the underlying semiconductor layer. Preferably, the method is applied to the formation of lightly doped so... | 06/25/2002 |
| 6410952 | MOSFET with a thin gate insulating film A semiconductor device comprises: a p-type semiconductor substrate (1); an insulating film (3); a gate electrode (2) formed on the substrate via the insulating film; and an n-type source/drain region (5) formed on both sides of a channel forming region (4... | 06/25/2002 |
| 6387782 | Process of forming an ultra-shallow junction dopant layer having a peak concentration within a dielectric layer A process for forming an ultra-shallow junction depth, doped region within a silicon substrate. The process includes forming a dielectric film on the substrate, then implanting an ionic dopant species into the structure. The profile of the implanted speci... | 05/14/2002 |
| 6362075 | Method for making a diffused back-side layer on a bonded-wafer with a thick bond oxide Integrated circuits, semiconductor devices and methods for making the same are described. Each embodiment shows a diffused, doped backside layer in a device wafer that is oxide bonded to a handle wafer. The diffused layer may originate in the device wafer... | 03/26/2002 |
| 6352591 | Methods and apparatus for shallow trench isolation The present invention provides systems, methods and apparatus for high temperature (at least about 500-800° C.) processing of semiconductor wafers. The systems, methods and apparatus of the present invention allow multiple process steps to be performed i... | 03/05/2002 |
| 6348385 | Method for a short channel CMOS transistor with small overlay capacitance using in-situ doped spacers with a low dielectric constant The method for a transistor using a replacement gate process that has a doped low-K dielectric spacer that lowers the junction capacitance. A dummy gate is formed over a substrate. Ions are implanted into the substrate using the dummy gate as an implant m... | 02/19/2002 |
| 6342313 | Oxide films and process for preparing same A p-type oxide film and a process for preparing the film and p-n or n-p junctions is disclosed. In a preferred embodiment, a p-type zinc oxide film contains arsenic and is grown on a gallium arsenide substrate. The p-type oxide film has a net acceptor con... | 01/29/2002 |
| 6333245 | Method for introducing dopants into semiconductor devices using a germanium oxide sacrificial layer A method for introducing dopants into a semiconductor device using doped germanium oxide is disclosed. The method includes using rapid thermal anneal (RTA) or furnace anneal to diffuse dopants into a substrate from a doped germanium oxide sacrificial laye... | 12/25/2001 |
| 6329704 | Ultra-shallow junction dopant layer having a peak concentration within a dielectric layer A process for forming an ultra-shallow junction depth, doped region within a silicon substrate. The process includes forming a dielectric film on the substrate, then implanting an ionic dopant species into the structure. The profile of the implanted speci... | 12/11/2001 |
| 6316310 | Method of forming a buried plate Known methods for forming trench storage capacitors require the chemical vapour deposition (CVD) of an undoped silicon oxide layer in order to prevent auto doping of side wall of a semiconductor trench. This layer is deposited once an arsenic doped silico... | 11/13/2001 |
| 6303453 | Method of manufacturing a semiconductor device comprising a MOS transistor The invention relates to a method of manufacturing a (horizontal) MOST, as used, for example, in (BI)CMOS ICs. On either side of a gate electrode (2), the surface of a silicon substrate (10, 11) which is positioned above a gate oxide (IA) is provided with... | 10/16/2001 |
| 6300228 | Multiple precipitation doping process A multiple precipitation doping process for doping a semiconductor substrate (30) starts with forming an amorphous region (32) in the substrate (30). Through multiple laser exposures, multiple dopant precipitation films (52, 53) are formed on correspondin... | 10/09/2001 |
| 6291085 | Zinc oxide films containing P-type dopant and process for preparing same A p-type zinc oxide film and a process for preparing the film is disclosed. In a preferred embodiment, the p-type zinc oxide film contains arsenic and is grown on a gallium arsenide substrate. The p-type zinc oxide film has a net acceptor concentration of... | 09/18/2001 |
| 6251755 | High resolution dopant/impurity incorporation in semiconductors via a scanned atomic force probe The present invention employs a scanned atomic force probe to physical incorporate impurity atoms (dopant or bandgap) into a semiconductor substrate so that the impurity atoms have high resolution and improved placement. Specifically, the method of the pr... | 06/26/2001 |
| 6245615 | Method and apparatus on (110) surfaces of silicon structures with conduction in the <110> direction Improved methods and structures are provided that are lateral to surfaces with a (110) crystal plane orientation such that an electrical current of such structures is conducted in the direction. Advantageously, improvements in hole carrier mobility ... | 06/12/2001 |
| 6238985 | Semiconductor device and method for fabricating the same A semiconductor device is disclosed, including: a semiconductor substrate; a gate electrode formed on the semiconductor substrate; a first gate insulating layer formed between the gate electrode and semiconductor substrate, and formed at a first region in... | 05/29/2001 |
| 6232207 | Doping process for producing homojunctions in semiconductor substrates In doping process for producing homojunctions in a semiconductor substrate, and the semiconductor substrate, dopants penetrate by way of diffusion employing an ultraviolet light source. A mask is introduced between the light source and the semiconductor w... | 05/15/2001 |
| 6229164 | MOSFET with a thin gate insulating film A semiconductor device comprises: a p-type semiconductor substrate (1); an insulating film (3); a gate electrode (2) formed on the substrate via the insulating film; and an n-type source/drain region (5) formed on both sides of a channel forming region (4... | 05/08/2001 |
| 6218714 | Insulated gate semiconductor device and method of manufacturing the same Dot-pattern-like impurity regions 104 are artificially and locally formed on a channel forming region 103. The impurity regions 104 restrain the expansion of a drain side depletion layer toward the channel forming region 103 to prevent the short channel e... | 04/17/2001 |
