Class 257/E21.147 - By ion implantation (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.146. This subclass
No. of patents: 84
Last issue date: 10/28/2008

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Number	Title	Issue Date
7442631	Doping method and method of manufacturing field effect transistor A doping method comprising the steps of; obtaining a proportion X of ions of a compound including a donor or an acceptor impurity in total ions from mass spectrum by using a first source gas of a first concentration; analyzing a peak concentration Y of the compound ...	10/28/2008
7416948	Trench FET with improved body to gate alignment A field effect transistor is formed as follows. Trenches are formed in a semiconductor region of a first conductivity type. Each trench is partially filled with one or more materials. A dual-pass angled implant is carried out to implant dopants of a second conductiv...	08/26/2008
7407874	Plasma doping method A plasma doping method that can control a dose precisely is realized. In-plane uniformity of the dose is improved. It has been found that, if a bias is applied by irradiating B2H6/He plasma onto a silicon substrate, there is a time at wh...	08/05/2008
7348264	Plasma doping method A plasma doping method that can control a dose precisely is realized. In-plane uniformity of the dose is improved. It has been found that, if a bias is applied by irradiating B2H6/He plasma onto a silicon substrate, there is a time at which a d...	03/25/2008
7303967	Method for fabricating transistor of semiconductor device Disclosed is a method for fabricating a transistor of a semiconductor device, the method comprising the steps of: providing a semiconductor; forming a gate electrode; performing a low-density ion implantation process with respect to the substrate, thereby forming an...	12/04/2007
7250312	Doping method and method for fabricating thin film transistor It is an object of the present invention to provide a doping apparatus, a doping method, and a method for fabricating a thin film transistor that can carry out doping to the carrier concentration which is optimum for obtaining the desired electric characteristic non...	07/31/2007
7189620	Semiconductor device including a channel stop structure and method of manufacturing the same It is an object to obtain a semiconductor device comprising a channel stop structure which is excellent in an effect of stabilizing a breakdown voltage and a method of manufacturing the semiconductor device. A silicon oxide film (2) is formed on an upper surf...	03/13/2007
7087503	Shallow self isolated doped implanted silicon process A process and structure for forming electrical devices. The process and structure provide for forming an insulating layer on a substrate. A conductive region is then formed in the insulating layer by implanting silicon atoms into the insulating layer. Further, a plu...	08/08/2006
6667513	Semiconductor device with compensated threshold voltage and method for making same A semiconductor device may include a channel region formed between a source and a drain region. One or more first pockets may be formed in the channel region adjacent to junctions. The first pockets may be doped with a dopant of the first conductivity typ...	12/23/2003
6600193	Trench MOSFET having implanted drain-drift region A trench MOSFET is formed in a structure which includes a P-type epitaxial layer overlying an N+ substrate. An N-type dopant is implanted through the bottom of the trench into the P-epitaxial layer to form a buried layer below the trench, and after a up-d...	07/29/2003
6555894	Device with patterned wells and method for forming same In a semiconductor substrate having a top surface and a PN junction between a first region of one conductivity type formed by masked diffusion into a semiconductor from the surface and a second region of opposite conductivity type formed into a first port...	04/29/2003
6552411	DC or AC electric field assisted anneal A method for forming a desired junction profile in a semiconductor device. At least one dopant is introduced into a semiconductor substrate. The at least one dopant is diffused in the semiconductor substrate through annealing the semiconductor substrate a...	04/22/2003
6509250	Method for CMOS well drive in a non-inert ambient Disclosed is an improved CMOS fabrication method that allows an implanted well in a bare silicon wafer to be simultaneously, driven annealed and denuded in a single process step. More specifically, a single step drive-anneal-denude (DAD) process is accomp...	01/21/2003
6507058	Low threshold compact MOS device with channel region formed by outdiffusion of two regions and method of making same A compact metal oxide semiconductor (MOS) device has its channel region formed by the lateral extension of two high voltage (HV) regions. The two HV regions are implanted into a well region and, as a result of an annealing process, undergo outdiffusion an...	01/14/2003
6500723	Method for forming a well under isolation and structure thereof A number of small wells under the isolation layer are formed using the same mask made of photoresist and implant step that is used for the regular wells. The small wells are formed close enough together so that they merge during normal subsequent semicond...	12/31/2002
6444551	N-type buried layer drive-in recipe to reduce pits over buried antimony layer A method of driving-in antimony into a wafer, including the following steps. A wafer is loaded into an annealing furnace/tool. The wafer having an area of implanted antimony ions. The wafer is annealed a first time at a first temperature in the presence o...	09/03/2002
6342435	Method for CMOS well drive in a non-inert ambient Disclosed is an improved CMOS fabrication method that allows an implanted well in a bare silicon wafer to be simultaneously, driven annealed and denuded in a single process step. More specifically, a single step drive-anneal-denude (DAD) process is accomp...	01/29/2002
6297120	Method of manufacturing a semiconductor device To provide a method of manufacturing a semiconductor device in which an epitaxial growth film is formed on a semiconductor substrate having a buried layer, which is capable of reducing the manufacturing time of the semiconductor device or reducing the IC ...	10/02/2001
6274465	DC electric field assisted anneal A method for forming a desired junction profile in a semiconductor device. At least one dopant is introduced into a semiconductor substrate. The at least one dopant is diffused in the semiconductor substrate through annealing the semiconductor substrate a...	08/14/2001
6268298	Method of manufacturing semiconductor device In a method of manufacturing a semiconductor device, after performing ion-implantation and before forming an oxide film, a silicon substrate is disposed within a furnace to undergo a heat treatment at a temperature equal to or higher than 950° C. for a s...	07/31/2001
6221719	Process for the manufacturing of a DMOS-technology transistor providing for a single thermal process for the formation of source and body regions Process for the manufacturing of a DMOS-technology transistor, providing for forming, over a semiconductor material layer of a first conductivity type, an insulated gate electrode, introducing in said semiconductor material layer a first dopant of a secon...	04/24/2001
6090669	Fabrication method for high voltage devices with at least one deep edge ring A fabrication method for high voltage power devices with at least one deep edge ring includes the steps of growing a lightly doped N-type epitaxial layer on a heavily doped N-type substrate, growing an oxide on the upper portion of the epitaxial layer, ma...	07/18/2000
6080630	Method for forming a MOS device with self-compensating V_T -implants The present invention provides a method for forming a MOS device having self-compensating threshold adjust implants and reduced junction capacitance. A semiconductor substrate of a first conductivity type is provided. A gate oxide is formed on the surface...	06/27/2000
6004868	Method for CMOS well drive in a non-inert ambient Disclosed is an improved CMOS fabrication method that allows an implanted well in a bare silicon wafer to be simultaneously, driven annealed and denuded in a single process step. More specifically, a single step drive-anneal-denude (DAD) process is accomp...	12/21/1999
5973381	MOS capacitor and MOS capacitor fabrication method A MOS capacitor has a p-type silicon substrate, an n-type impurity diffusion area formed by implanting an impurity into a region of the silicon substrate, a silicon oxide layer formed on the diffusion area, and a polysilicon electrode formed on the silico...	10/26/1999
5899732	Method of implanting silicon through a polysilicon gate for punchthrough control of a semiconductor device A region of damaged silicon is exploited as a gettering region for gettering impurities in a silicon substrate. The region of damaged silicon is formed between source and drain regions of a device by implanting silicon atoms into the silicon substrate aft...	05/04/1999
5814541	Method for manufacturing semiconductor device A method of manufacturing semiconductor devices yielding devices having impurity regions that are more shallow and exhibit less lateral diffusion than devices manufactured in accordance with prior art techniques. First, arsenic is introduced into a substr...	09/29/1998
5677208	Method for making FET having reduced oxidation inductive stacking fault An improved manufacturing method for a semiconductor device, which can reduce process inductive fault such as oxidation inductive stacking fault (OSF) and contribute to the improvement of the electric characteristics of the semiconductor device, is disclo...	10/14/1997
5668020	Method for forming impurity junction regions of semiconductor device A method for forming impurity junction regions of a semiconductor device wherein impurity junction regions with a small depth are formed by selectively forming defecting regions and amorphous regions in a semiconductor substrate by an implantation of impu...	09/16/1997
5605851	Method of forming semiconductor device with a buried junction A method is disclosed for forming a first region with conductivity of a first type and second, buried region with conductivity of a second type which forms a junction with the first region. By first and second doping steps, impurities of a first and a sec...	02/25/1997
5578506	Method of fabricating improved lateral Silicon-On-Insulator (SOI) power device A high performance lateral Silicon-On-Insulator (SOI) power device having a high breakdown voltage (ࣘ100 v). The SOI power device includes a silicon layer formed on an oxide layer over a silicon substrate. A mask having a single opening on the anode (dr...	11/26/1996
5418184	Method of manufacturing a semiconductor device in which dopant atoms are provided in a semiconductor body A method of manufacturing a semiconductor device includes the step of providing a dopant (4) near a surface (2) of a semiconductor body (1) in a deposition step, after which in a diffusion step the dopant (4) is diffused into the semiconductor body (1) by...	05/23/1995
5312764	Method of doping a semiconductor substrate A method of decoupling a step for modulating a defect density from a step for modulating a junction depth. A semiconductor substrate (30) having a portion doped with a dopant (34) is heated to a pre-oxidation anneal temperature in a pre-oxidation anneal s...	05/17/1994
5300454	Method for forming doped regions within a semiconductor substrate A method for forming a first doped region (24) and a second doped region (26) within a substrate (12). A masking layer (14) overlies the substrate (12). A first region (20) of the masking layer (14) is etched to form a first plurality of openings. A secon...	04/05/1994
5256563	Doped well structure and method for semiconductor technologies A method of forming doped wells 24 and 30 in a semiconductor layer is disclosed herein. In a preferred embodiment, an oxide layer 16 is formed on the surface of a silicon layer 14. A nitride layer 18 is then formed on the oxide layer 16 and is patterned a...	10/26/1993
5219783	Method of making semiconductor well structure A method of forming doped well regions in a semiconductor layer 14 is disclosed herein. At least one n-doped region 30 and at least one p-doped region 36 are formed in the semiconductor layer 14. The n-doped region 30 is separated from the p-doped region ...	06/15/1993
5217924	Method for forming shallow junctions with a low resistivity silicide layer A method for forming a shallow junction (56) with a relatively thick metal silicide (52) thereover is provided. A first relatively thin layer (38) of a metal is deposited over the surface of a semiconductor substrate. An impurity (40) is then implanted (4...	06/08/1993
5192712	Control and moderation of aluminum in silicon using germanium and germanium with boron A process is disclosed for controlling the diffusion of aluminum in silicon for the fabrication of monolithic pn junction isolated integrated circuits. Germanium is incorporated into the silicon where isolation or p-well diffusion of aluminum is to occur....	03/09/1993
5187117	Single diffusion process for fabricating semiconductor devices A simplified process of making an insulated gate transistor entails forming the active regions in a single diffusion step. The method includes the steps of implanting and diffusing impurities of a first conductivity type (p for n-channel devices), implant...	02/16/1993
5130261	Method of rendering the impurity concentration of a semiconductor wafer uniform According to this invention, there is provided to a method of manufacturing semiconductor devices including the steps of ion-implanting at least one impurity selected from As, P, Sb, Si, B, Ga, and Al in a wafer prior to a predetermined manufactural proce...	07/14/1992

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Class 257/E21.147 - By ion implantation (EPO)