Class 257/E21.144 - Using diffusion into or out of a s olid from or into a solid phase, e.g., a doped oxide layer (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.135. This subclass
No. of patents: 22
Last issue date: 10/21/2008

Number	Title	Issue Date
7439609	Doping of gallium nitride by solid source diffusion and resulting gallium nitride structures An improved p-type gallium nitride-based semiconductor device is disclosed. The device includes a structure with at least one p-type Group III nitride layer that includes some gallium, a first silicon dioxide layer on the p-type layer, a layer of a Group II metal so...	10/21/2008
7326631	Method of manufacturing MOS transistors with gate electrodes formed in a packet of metal layers deposited upon one another Consistent with an example embodiment, a method of manufacturing a semiconductor device comprises MOS transistors having gate electrodes formed in a number of metal layers deposited upon one another. Active silicon regions having a layer of a gate dielectric and fie...	02/05/2008
7303967	Method for fabricating transistor of semiconductor device Disclosed is a method for fabricating a transistor of a semiconductor device, the method comprising the steps of: providing a semiconductor; forming a gate electrode; performing a low-density ion implantation process with respect to the substrate, thereby forming an...	12/04/2007
7282428	Method for solid phase diffusion of zinc into an InP-based photodiode and an InP photodiode made with the method In order to form a p-region in an InP-based photodiode, zinc doping must be performed. Due to the current trend toward the implementation of larger-sized InP wafers, there is a need for a solid phase diffusion method in which a ZnO thin film is applied to an epitaxi...	10/16/2007
6531379	High resolution dopant/impurity incorporation in semiconductors via a scanned atomic force probe The present invention employs a scanned atomic force probe to physical incorporate impurity atoms (dopant or bandgap) into a semiconductor substrate so that the impurity atoms have high resolution and improved placement. Specifically, the method of the pr...	03/11/2003
6251755	High resolution dopant/impurity incorporation in semiconductors via a scanned atomic force probe The present invention employs a scanned atomic force probe to physical incorporate impurity atoms (dopant or bandgap) into a semiconductor substrate so that the impurity atoms have high resolution and improved placement. Specifically, the method of the pr...	06/26/2001
4907059	Semiconductor bipolar-CMOS inverter A semiconductor device has a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type; an interconnection layer, containing an impurity of a second conductivity type, for connecting the first and...	03/06/1990
4757027	Method for fabricating improved oxide defined transistors Two insulating layers may be employed to define boundaries of junctions in transistor structures useful in integrated circuit fabrication. The junctions may overlie one another, have approximately equal areas, and terminate in the insulating layers....	07/12/1988
4720308	Method for producing high-aspect ratio hollow diffused regions in a semiconductor body and diode produced thereby A semiconductor device and a method for its preparation are disclosed, wherein a body of semiconducting material has at least one bore extending completely therethrough, this bore having a substantially constant diameter of less than about 1.5 mils and an...	01/19/1988
4712125	Structure for contacting a narrow width PN junction region A method and resulting structure for making contact to a narrow width PN junction region in any desired semiconductor body is described. A substantially vertical conformal conductive layer is formed over the desired PN junction region. The body is heated ...	12/08/1987
4692348	Low temperature shallow doping technique A technique is described for producing very shallow doped regions in a substrate, at low temperatures. The doped regions are not in excess of about 300 angstroms in depth, and are formed at temperatures less than 700° C. These shallow doped regions can b...	09/08/1987
4676847	Controlled boron doping of silicon A technique is described for doping a silicon body with boron. The surface to be doped is typically a trench sidewall, to be used as a storage capacitor or for isolation. By providing a silicon dioxide diffusion control layer, and a polysilicon source lay...	06/30/1987
4626293	Method of making a high voltage DMOS transistor A process for manufacturing a high voltage DMOS (Deep Diffusion Metal Oxide Semiconductor) transistor includes a first ion implantation and drive-in step to form a P-well in a N-substrate, and a second such step to form a N+ region in this well and a chan...	12/02/1986
4619719	Process for forming a doped oxide film and composite article A process for forming a doped oxide film suitable for doping a semiconductor wafer substrate material and composite article. A silicon tetra-alkoxide is reacted with a limited amount of water to produce a low molecular weight, soluble polyorganosiloxane. ...	10/28/1986
4605450	Process for forming a doped oxide film and doped semiconductor A process for forming a doped oxide film and a doped semiconductor suitable for electronic applications wherein a silicon tetraalkoxide is reacted with a limited amount of water to produce a low molecular weight, soluble polyorganosiloxane. The polyorgano...	08/12/1986
4578283	Polymeric boron nitrogen dopant A polymeric borazole is produced by reacting BCl3 and an amine at temperatures between -60° C. and -5° C. in an inert solvent to form an intermediate triaminoborane, and then further polymerizing the intermediate after removal of the amine hy...	03/25/1986
4529456	Method of forming bifets by forming isolation regions connected by diffusion in semiconductor substrate and epitaxial layer The present invention relates to a method of manufacturing a semiconductor integrated circuit device, especially a Bi-MOS IC. It comprises: 1. introducing an impurity of a first conductivity type into a plurality of parts of one major surface of a substrate co...	07/16/1985
4485552	Complementary transistor structure and method for manufacture Disclosed is a method of making on a common substrate complementary vertical NPN and PNP transistors having matched high performance characteristics. A barrier region of a first conductivity type is formed on a semiconductor substrate of a second conducti...	12/04/1984
4471524	Method for manufacturing an insulated gate field effect transistor device An overall method for manufacturing an IGFET device having extremely shallow source and drain regions and reduced gate to source and drain overlap capacitances is disclosed. For silicon MOS devices, the method also provides for the formation of metal sili...	09/18/1984
4472212	Method for fabricating a semiconductor device A method for forming a shallow and highly concentrated arsenic doped surface layer in a silicon bulk region includes the steps of forming an arsenic doped polysilicon layer in contact with a preselected area of a bulk region surface in which the surface l...	09/18/1984
4435225	Method of forming self-aligned lateral bipolar transistor A lateral bipolar transistor having a base width of 0.5 micron or less is made by forming a protective layer on an electrically insulating layer along a surface of a semiconductor body, forming an open space through the protective layer so as to define a ...	03/06/1984
4050966	Method for the preparation of diffused silicon semiconductor components A method for preparing semiconductor components from silicon as the base material. The components have at least two zones, produced by diffusion, with different conduction type. The diffusion of the individual zones takes place from dopant containing nick...	09/27/1977

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Class 257/E21.144 - Using diffusion into or out of a s olid from or into a solid phase, e.g., a doped oxide layer (EPO)