Class 257/E21.135 - Diffusion of impurity material, e.g., doping material, electrode material, into or out of a semiconductor body, or between semiconductor regions; interactions between two or more impurities; redistribution of impurities (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.085. This subclass
No. of patents: 88
Last issue date: 10/28/2008

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Number	Title	Issue Date
7442613	Methods of forming an asymmetric field effect transistor A field effect transistor includes a channel region under a gate stack formed on a semiconductor structure. The field effect transistor also includes a drain region formed with a first dopant doping a first side of the channel region, and includes a source region fo...	10/28/2008
7439165	Method of fabricating tensile strained layers and compressive strain layers for a CMOS device A process for forming both tensile and compressive strained silicon layers to accommodate channel regions of MOSFET or CMOS devices has been developed. After formation of shallow trench isolation structures as well as application of high temperature oxidation and ac...	10/21/2008
7422943	Semiconductor device capacitors with oxide-nitride layers and methods of fabricating such capacitors Capacitors having upper electrodes that include a lower electrode, a dielectric layer and an upper electrode that includes a conductive metal nitride layer and a doped polysilicon germanium layer are provided. At least part of the conductive metal nitride layer is o...	09/09/2008
7416934	Semiconductor device A dose of arsenic for an extension region in an NMOS transistor is in a range from 5×1014 to 2×1015 ions/cm2 and preferably in a range from 1.1×1015 to 1.5×1015 ions/cm2. Also, in addition to arse...	08/26/2008
7405110	Methods of forming implant regions relative to transistor gates The invention includes methods of forming implant regions between and/or under transistor gates. In one aspect, a pair of transistor gates is partially formed, and a layer of conductive material is left extending between the transistor gates. A dopant is implanted t...	07/29/2008
7396758	Polycarbosilane buried etch stops in interconnect structures Interconnect structures having buried etch stop layers with low dielectric constants and methods relating to the generation of such buried etch stop layers are described herein. The inventive interconnect structure comprises a buried etch stop layer comprised of a p...	07/08/2008
7390680	Method to selectively identify reliability risk die based on characteristics of local regions on the wafer A method and system for selectively identifying reliability risk die based on characteristics of local regions on a wafer by computing particle sensitive yield and using the particle sensitive yield to identify reliability risk die. Specifically, a bin characteristi...	06/24/2008
7368370	Site-specific nanoparticle self-assembly Disclosed herein are methods of self-assembling nanoparticles on specific sites of a substrate. The method generally includes introducing a p-type dopant species to at least a portion of an n-type substrate or introducing an n-type dopant species to at least a porti...	05/06/2008
7354841	Method for fabricating photodiode of CMOS image sensor A method for fabricating a photodiode of a CMOS image sensor is disclosed, to improve a charge accumulation capacity in the photodiode, which includes the steps of defining a semiconductor substrate as an active area and a field area by forming an STI layer; firstly...	04/08/2008
7314788	Standard cell back bias architecture An apparatus including, in one embodiment, a CMOS device cell including at least first and second CMOS transistors having first and second CMOS transistor doped regions in first and second doped wells, respectively, wherein each of the first and second CMOS transist...	01/01/2008
7312483	Thin film transistor device and method of manufacturing the same A semiconductor film is formed on a substrate. Subsequently, a resist film is formed on the semiconductor film, and dry etching is performed to the semiconductor film using the resist film as a mask. Due to the dry etching, the edge portion of the semiconductor film...	12/25/2007
7303967	Method for fabricating transistor of semiconductor device Disclosed is a method for fabricating a transistor of a semiconductor device, the method comprising the steps of: providing a semiconductor; forming a gate electrode; performing a low-density ion implantation process with respect to the substrate, thereby forming an...	12/04/2007
7297603	Bi-directional transistor and method therefor In one embodiment, a transistor is formed to conduct current in both directions through the transistor. ...	11/20/2007
7297994	Semiconductor device having a retrograde dopant profile in a channel region An epitaxially grown channel layer is provided on a well structure after ion implantation steps and heat treatment steps are performed to establish a required dopant profile in the well structure. The channel layer may be undoped or slightly doped, as required, so t...	11/20/2007
7262066	Systems and methods for thin film thermal diagnostics with scanning thermal microstructures Systems and methods are described for identifying characteristics and defects in material such as semiconductors. Methods include scanning a thermal probe in the vicinity of a semiconductor sample, applying stimuli to the thermal probe, and monitoring the interactio...	08/28/2007
7232729	Method for manufacturing a double bitline implant The present invention provides a method of fabricating a doped semiconductor region comprising selectively implanting a first impurity to form a shallow heavily doped region. The method further comprises selectively implanting the first impurity to also form a deep ...	06/19/2007
7208330	Method for varying the uniformity of a dopant as it is placed in a substrate by varying the speed of the implant across the substrate The present invention provides a method for placing a dopant in a substrate and a method for manufacturing an integrated circuit. The method for placing a dopant in a substrate, among other steps, includes providing a substrate (340) and implanting a dopant w...	04/24/2007
7179728	Optical component and manufacturing method thereof, microlens substrate and manufacturing method thereof, display device, and imaging device The invention provides an optical component whose siting, shape and size are well controlled and a method of manufacturing such an optical component. The optical component of the present invention includes a base member disposed on a substrate, and an optical member...	02/20/2007
7176113	LDC implant for mirrorbit to improve Vt roll-off and form sharper junction The present invention pertains to implementing a lightly doped channel (LDC) implant in fashioning a memory device to improve Vt roll-off, among other things. The lightly doped channel helps to preserve channel integrity such that a threshold voltage (Vt) can be mai...	02/13/2007
7138322	Semiconductor device and fabrication method therefor An n-type channel diffused layer and an n-type well diffused layer are formed in the top portion of a semiconductor substrate, and a gate insulating film and a gate electrode are formed on the semiconductor substrate. Using the gate electrode as a mask, boron and ar...	11/21/2006
7098120	Method of manufacturing semiconductor devices A method of manufacturing semiconductor devices includes forming element isolation regions in a semiconductor substrate, a gate insulation film in an element region surrounded by the element isolation regions and an impurity doped metal silicide film on the gate ins...	08/29/2006
6646304	Universal semiconductor wafer for high-voltage semiconductor components A universal semiconductor wafer for high-voltage semiconductor components includes at least one layer of a first conductivity type which is provided on a semiconductor substrate of the first conductivity type. A plurality of floating semiconductor zones o...	11/11/2003
6294415	Method of fabricating a MOS transistor An improved method of fabricating a MOS transistor on a semiconductor wafer is disclosed. A pre-amorphization implant (PAI) process is used to dope the silicon substrate adjacent to the gate. The dopants formed in the silicon substrate during the first io...	09/25/2001
6153920	Process for controlling dopant diffusion in a semiconductor layer and semiconductor device formed thereby A semiconductor device having a carbon-containing region with an advantageous concentration profile is disclosed. The carbon is introduced into a region of the substrate and at a depth below the space-charge layer of the device and at a concentration such...	11/28/2000
6043139	Process for controlling dopant diffusion in a semiconductor layer Diffusion of ion-implanted dopant is controlled by incorporating electrically inactive impurity in a semiconductor layer by at least one crystal growth technique....	03/28/2000
5871826	Proximity laser doping technique for electronic materials This invention relates to a method of altering the electrical characteristics of a material through a laser ablation process. It can achieve high doping levels and shallow junctions at low temperatures, which are desirable in the fabrication of thin film ...	02/16/1999
5814541	Method for manufacturing semiconductor device A method of manufacturing semiconductor devices yielding devices having impurity regions that are more shallow and exhibit less lateral diffusion than devices manufactured in accordance with prior art techniques. First, arsenic is introduced into a substr...	09/29/1998
5731626	Process for controlling dopant diffusion in a semiconductor layer and semiconductor layer formed thereby Diffusion of ion-implanted dopant is controlled by incorporating electrically inactive impurity in a semiconductor layer by at least one crystal growth technique....	03/24/1998
5654209	Method of making N-type semiconductor region by implantation A semiconductor device at least including a region which contains a first impurity constituted by a group V element and a second impurity constituted by an element of high electronegativity or a halogen element such as Ti, Cl, O, Br, S, I or N in amorphou...	08/05/1997
5565377	Process for forming retrograde profiles in silicon A process for forming retrograde and oscillatory profiles in crystalline and polycrystalline silicon. The process consisting of introducing an n- or p-type dopant into the silicon, or using prior doped silicon, then exposing the silicon to multiple pulses...	10/15/1996
5557141	Method of doping, semiconductor device, and method of fabricating semiconductor device A group III-V compound semiconductor doped with an impurity, having an undoped film of SiOx and a film for preventing the diffusion of Group V atoms (e.g., an SiN film) are formed on a crystal of Group III-V compound semiconductor in which the silicon in ...	09/17/1996
5543356	Method of impurity doping into semiconductor A method of impurity doping into a semiconductor, which comprises irradiating energy rays such as excimer laser beam (or UV-rays) to a predetermined region of a hydrogen terminated silicon surface to remove hydrogen atom layers terminating the silicon sur...	08/06/1996
5506169	Method for reducing lateral dopant diffusion A process is disclosed for inhibiting lateral diffusion of dopants in a semiconductive material. At least one conductivity dependent region is formed in the semiconductor, and a blocking layer is provided in overlying relation with the conductivity depend...	04/09/1996
5432377	Dielectrically isolated semiconductor device and a method for its manufacture A semiconductor device is supported by a semiconductor body which comprises a substrate, an oxide layer and a weakly doped monocrystalline wafer. Trenches for a dielectrically isolating layer which surrounds a component region are etched in the wafer. A f...	07/11/1995
5356829	Silicon device including a pn-junction acting as an etch-stop in a silicon substrate The method of making a silicon device including a pn-junction includes the steps of providing a p-doped monocrystalline silicon substrate (1) with a doping concentration CS ; making a pn-junction by forming a first n-doped layer portion (21) di...	10/18/1994
5350709	Method of doping a group III-V compound semiconductor A method of doping a Group III-V compound semiconductor with an impurity, wherein after an undoped film of SiOx and a film for preventing the diffusion of Group V atoms (e.g., an SiN film) are formed in this order on a crystal of Group III-V compound semi...	09/27/1994
5316958	Method of dopant enhancement in an epitaxial silicon layer by using germanium An in-situ doped n-type silicon layer is provided by a low temperature, low pressure chemical vapor deposition process employing a germanium-containing gas in combination with the n-type dopant containing gas to thereby enhance the in-situ incorporation o...	05/31/1994
5298435	Application of electronic properties of germanium to inhibit n-type or p-type diffusion in silicon A method of inhibiting dopant diffusion in silicon using germanium is provided. Germanium is distributed in substitutional sites in a silicon lattice to form two regions of germanium interposed between a region where dopant is to be introduced and a regio...	03/29/1994
5284783	Method of fabricating a heterojunction bipolar transistor A method of fabricating a semiconductor device having an epitaxial layer of a group III-V semiconductor material provided on an underlying crystal layer with a lattice matching therewith, the semiconductor material being doped to the p-type by addition of...	02/08/1994
5280185	Application of electronic properties of germanium to inhibit n-type or p-type diffusion in silicon A structure of inhibiting dopant diffusion in silicon using germanium is provided. Germanium is distributed in substitutional sites in a silicon lattice to form two regions of germanium interposed between a region where dopant is to be introduced and a re...	01/18/1994

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Class 257/E21.135 - Diffusion of impurity material, e.g., doping material, electrode material, into or out of a semiconductor body, or between semiconductor regions; interactions between two or more impurities; redistribution of impurities (EPO)