Class 257/E21.129 - Group IVA, e.g., Si, C, Ge on Group IVB, e.g., Ti, Zr (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.124. This subclass
No. of patents: 41
Last issue date: 09/23/2008

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Number	Title	Issue Date
7427811	Semiconductor substrate A semiconductor wafer having a high degree of thinness and exhibiting an enhanced strength state. A layer of tenacious reinforcement material is disposed over a back side of the wafer while in a rough state from backgrinding without prior, conventional polishing or ...	09/23/2008
7410917	Atomic layer deposited Zr-Sn-Ti-O films using TiI Various structures having a dielectric film containing Zr—Sn—Ti—O formed by atomic layer deposition using a TiI4 precursor and a method of fabricating structures having such a dielectric film produce the structures with a reliable dielectric layer h...	08/12/2008
7371637	Oxide-nitride stack gate dielectric A method of making a semiconductor structure comprises forming an oxide layer on a substrate; forming a silicon nitride layer on the oxide layer; annealing the layers in NO; and annealing the layers in ammonia. The equivalent oxide thickness of the oxide layer and t...	05/13/2008
7364980	Manufacturing method of semiconductor substrate Closure at the opening of a trench with an epitaxial film is restrained, and thereby, filling morphology in the trenches is improved. A method for manufacturing a semiconductor substrate includes a step for growing an epitaxial layer 11 on the surface of a si...	04/29/2008
7348260	Method for forming a relaxed or pseudo-relaxed useful layer on a substrate A method for forming a relaxed or pseudo-relaxed useful layer on a substrate is described. The method includes growing a strained semiconductor layer on a donor substrate, bonding a receiver substrate to the strained semiconductor layer by a vitreous layer of a mate...	03/25/2008
7332443	Method for fabricating a semiconductor device The present invention relates to a method for fabricating a semiconductor device. In order to provide for a high carrier mobility in an active region of the device, germanium atoms are implanted into a surface of a semiconductor substrate such that a germanium-conta...	02/19/2008
7271436	Flash memory devices including a pass transistor Flash memory integrated circuit devices include an integrated circuit substrate. A cell array on the integrated circuit substrate includes a plurality of cell transistors. A bit line is coupled to ones of the plurality of cell transistors and a first pass transistor...	09/18/2007
7241670	Method to form relaxed SiGe layer with high Ge content using co-implantation of silicon with boron or helium and hydrogen A method of forming a relaxed SiGe layer having a high germanium content in a semiconductor device includes preparing a silicon substrate; depositing a strained SiGe layer; implanting ions into the strained SiGe layer, wherein the ions include silicon ions and ions ...	07/10/2007
7229876	Method of fabricating memory A method of fabricating a memory device is described. During the process of forming the memory cell area and the periphery area of a semiconductor device a photoresist layer is formed on the memory cell area before the spacers are formed on the sidewalls of the gate...	06/12/2007
7223662	Method of forming an epitaxial layer for raised drain and source regions by removing surface defects of the initial crystal surface By substantially amorphizing a selectively epitaxially grown silicon layer used for forming a raised drain and source region and a portion of the underlying substrate, or just the surface region of the substrate (prior to growing the silicon overlayer), the number o...	05/29/2007
7217668	Gate technology for strained surface channel and strained buried channel MOSFET devices A method of fabricating a semiconductor device including providing a semiconductor heterostructure, the heterostructure having a relaxed Si1-xGex layer on a substrate, a strained channel layer on the relaxed Si1-xGex layer...	05/15/2007
7138309	Integration of biaxial tensile strained NMOS and uniaxial compressive strained PMOS on the same wafer A method of fabricating a biaxial tensile strained layer for NMOS fabrication and a uniaxial compressive strained layer for PMOS fabrication on a single wafer for use in CMOS ICs, includes preparing a silicon substrate for CMOS fabrication; depositing, patterning an...	11/21/2006
7122483	Gate technology for strained surface channel and strained buried channel MOSFET devices A method of fabricating a semiconductor device including providing a semiconductor heterostructure, the heterostructure having a relaxed Si1-xGex layer on a substrate, a strained channel layer on the relaxed Si1-xGex layer...	10/17/2006
6703144	Heterointegration of materials using deposition and bonding A semiconductor structure including a first substrate, and an epitaxial layer bonded to the substrate. The epitaxial layer has a threading dislocation density of less than 107 cm-2 and an in-plane lattice constant that is different f...	03/09/2004
6703688	Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic p...	03/09/2004
6703293	Implantation at elevated temperatures for amorphization re-crystallization of Si1-xGex films on silicon substrates A method of fabricating a Si1-X GeX film on a silicon substrate includes preparing a silicon substrate; epitaxially depositing a Si1-X GeX layer on the silicon substrate forming a Si1-X GeX...	03/09/2004
6699764	Method for amorphization re-crystallization of Si1-xGex films on silicon substrates A method of fabricating a Si1-X GeX film on a silicon substrate includes preparing a silicon substrate; epitaxially depositing a Si1-X GeX layer on the silicon substrate forming a Si1-X GeX...	03/02/2004
6693298	Structure and method for fabricating epitaxial semiconductor on insulator (SOI) structures and devices utilizing the formation of a compliant substrate for materials used to form same High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a la...	02/17/2004
6677192	Method of fabricating a relaxed silicon germanium platform having planarizing for high speed CMOS electronics and high speed analog circuits Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic p...	01/13/2004
6667102	Silicon layer highly sensitive to oxygen and method for obtaining same A highly oxygen-sensitive silicon layer (2) is formed on a substrate (4) of, for example, SiC. The layer (2) has a 4×3 surface structure. The silicon layer (2) is deposited on a surface of the substrate (4) in a substantially uniform manner. The highly o...	12/23/2003
6649492	Strained Si based layer made by UHV-CVD, and devices therein A method for fabricating a strained Si based layer, devices manufactured in this layer, and electronic systems comprising such layers and devices are disclosed. The method comprises the steps of growing epitaxially a SiGe layer on a substrate, and creatin...	11/18/2003
6646322	Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic p...	11/11/2003
6645836	Method of forming a semiconductor wafer having a crystalline layer thereon containing silicon, germanium and carbon A Si substrate 1 with a SiGeC crystal layer 8 deposited thereon is annealed to form an annealed SiGeC crystal layer 10 on the Si substrate 1. The annealed SiGeC crystal layer includes a matrix SiGeC crystal layer 7, which is lattice-relieved and hardly ha...	11/11/2003
6635110	Cyclic thermal anneal for dislocation reduction The invention provides processes for producing a very low dislocation density in heterogeneous epitaxial layers with a wide range of thicknesses, including a thickness compatible with conventional silicon CMOS processing. In a process for reducing disloca...	10/21/2003
6600203	Semiconductor device with silicon carbide suppression layer for preventing extension of micropipe A suppression layer is formed on a SiC substrate in accordance with a CVD method which alternately repeats the step of epitaxially growing an undoped layer which is a SiC layer into which an impurity is not introduced and the step of epitaxially growing a...	07/29/2003
6593641	Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic p...	07/15/2003
6576532	Semiconductor device and method therefor A heteroepitaxial structure is made using nanocrystals that are formed closer together than normal lithography patterning would allow. The nanocrystals are oxidized and thus selectively etchable with respect to the substrate and surrounding material. In o...	06/10/2003
6525338	Semiconductor substrate, field effect transistor, method of forming SiGe layer and method of forming strained Si layer using same, and method of manufacturing field effect transistor A semiconductor substrate, a field effect transistor, a method of forming a SiGe layer and a method of forming a strained Si layer using the same, and a method of manufacturing a field effect transistor are provided, which enable the threading dislocation...	02/25/2003
6515335	Method for fabrication of relaxed SiGe buffer layers on silicon-on-insulators and structures containing the same A method of fabricating relaxed SiGe buffer layers with low threading dislocation densities on silicon-on-insulator (SOI) substrates is provided. The relaxed SiGe buffer layers are fabricated by the epitaxial deposition of a defect-free Stranski-Krastanov...	02/04/2003
6447605	Method for preparing heteroepitaxial thin film Disclosed is a method for preparing heteroepitaxial thin films which are free of island structures which have a bad influence on the photoelectric properties and interfacial reactivity of the thin films. These heteroepitaxial thin films are deposited on g...	09/10/2002
6352942	Oxidation of silicon on germanium The invention provides processes for producing a high-quality silicon dioxide layer on a germanium layer. In one example process, a layer of silicon is deposited on the germanium layer, and the silicon layer is exposed to dry oxygen gas at a temperature t...	03/05/2002
6313017	Plasma enhanced CVD process for rapidly growing semiconductor films A process of epitaxially growing a Group IV semiconductor film on a surface (WS) of a substrate (W) made of a material comprising one of Si or Ge in a reaction chamber (14) under vacuum. The process includes the steps of heating the substrate to a tempera...	11/06/2001
6291321	Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization A semiconductor structure including a semiconductor substrate, at least one first crystalline epitaxial layer on the substrate, the first layer having a surface which is planarized, and at least one second crystalline epitaxial layer on the at least one f...	09/18/2001
6107653	Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization A semiconductor structure including a semiconductor substrate, at least one first crystalline epitaxial layer on the substrate, the first layer having a surface which is planarized, and at least one second crystalline epitaxial layer oil the at least one ...	08/22/2000
6059895	Strained Si/SiGe layers on insulator An SOI substrate and method for forming is described incorporating the steps of forming strained layers of Si and/or SiGe on a first substrate, forming a layer of Si and/or Si O2 over the strained layers, bonding a second substrate h...	05/09/2000
5906951	Strained Si/SiGe layers on insulator An SOI substrate and method for forming is described incorporating the steps of forming strained layers of Si and/or SiGe on a first substrate, forming a layer of Si and/or Si O2 over the strained layers, bonding a second substrate h...	05/25/1999
5102810	Method for controlling the switching speed of bipolar power devices The switching speed of bipolar power rectifiers is increased by formation of misfit dislocations in the depletion region, spaced from the substrate/epitaxial layer interface, in order to reduce minority carrier lifetime. The misfit dislocations are formed...	04/07/1992
5097308	Method for controlling the switching speed of bipolar power devices The switching speed of bipolar power rectifiers is increased by formation of misfit dislocations in the depletion region, spaced from the substrate/epitaxial layer interface, in order to reduce minority carrier lifetime. The misfit dislocations are formed...	03/17/1992
5089428	Method for forming a germanium layer and a heterojunction bipolar transistor A method for preparing a germanium layer (22) adjacent to a germanium silicon layer (20). Initially, a P-germanium silicon layer (16) is deposited on to an N-germanium silicon layer (14). The continuous germanium layer (22) is formed by heating the layers...	02/18/1992
4975387	Formation of epitaxial si-ge heterostructures by solid phase epitaxy Epitaxial Si-Ge heterostructures are formed by depositing a layer of amorphous Si-Ge on a silicon wafer. The amorphous Si-Ge on the silicon wafer is then subjected to a wet oxidation in order to form an epitaxial Si-Ge heterostructure. Any size wafer may ...	12/04/1990

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Class 257/E21.129 - Group IVA, e.g., Si, C, Ge on Group IVB, e.g., Ti, Zr (EPO)