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| Number | Title | Issue Date |
| 7442631 | Doping method and method of manufacturing field effect transistor A doping method comprising the steps of; obtaining a proportion X of ions of a compound including a donor or an acceptor impurity in total ions from mass spectrum by using a first source gas of a first concentration; analyzing a peak concentration Y of the compound ... | 10/28/2008 |
| 7375011 | Ex-situ doped semiconductor transport layer A method of making an ex-situ doped semiconductor transport layer for use in an electronic device includes: growing a first set of semiconductor nanoparticles having surface organic ligands in a colloidal solution; growing a second set of dopant material nanoparticl... | 05/20/2008 |
| 7329596 | Method for tuning epitaxial growth by interfacial doping and structure including same A method that allows for uniform, simultaneous epitaxial growth of a semiconductor material on dissimilarly doped semiconductor surfaces (n-type and p-type) that does not impart substrate thinning via a novel surface preparation scheme, as well as a structure that r... | 02/12/2008 |
| 7282381 | Method of producing self supporting substrates comprising III-nitrides by means of heteroepitaxy on a sacrificial layer The invention relates to a method for the production of self-supporting substrates comprising element III nitrides. More specifically, the invention relates to a method of producing a self-supporting substrate comprising a III-nitride, in particular, gallium nitride... | 10/16/2007 |
| 7241670 | Method to form relaxed SiGe layer with high Ge content using co-implantation of silicon with boron or helium and hydrogen A method of forming a relaxed SiGe layer having a high germanium content in a semiconductor device includes preparing a silicon substrate; depositing a strained SiGe layer; implanting ions into the strained SiGe layer, wherein the ions include silicon ions and ions ... | 07/10/2007 |
| 7186626 | Method for controlling dislocation positions in silicon germanium buffer layers A method for controlling dislocation position in a silicon germanium buffer layer located on a substrate includes depositing a strained silicon germanium layer on the substrate and irradiating one or more regions of the silicon germanium layer with a dislocation ind... | 03/06/2007 |
| 7160804 | Method of fabricating MOS transistor by millisecond anneal A method of fabricating a MOS transistor by millisecond annealing. A semiconductor substrate with a gate stack comprising a gate electrode overlying a gate dielectric layer on a top surface of a semiconductor substrate is provided. At least one implanting process is... | 01/09/2007 |
| 7084051 | Manufacturing method for semiconductor substrate and manufacturing method for semiconductor device A purpose of the invention is to provide a manufacturing method for a semiconductor substrate in which a high quality strained silicon channel can easily be formed without sacrificing the processing efficiency of a wafer and to provide a manufacturing method for a s... | 08/01/2006 |
| 6703293 | Implantation at elevated temperatures for amorphization re-crystallization of Si1-xGex films on silicon substrates A method of fabricating a Si1-X GeX film on a silicon substrate includes preparing a silicon substrate; epitaxially depositing a Si1-X GeX layer on the silicon substrate forming a Si1-X GeX... | 03/09/2004 |
| 6699764 | Method for amorphization re-crystallization of Si1-xGex films on silicon substrates A method of fabricating a Si1-X GeX film on a silicon substrate includes preparing a silicon substrate; epitaxially depositing a Si1-X GeX layer on the silicon substrate forming a Si1-X GeX... | 03/02/2004 |
| 6693298 | Structure and method for fabricating epitaxial semiconductor on insulator (SOI) structures and devices utilizing the formation of a compliant substrate for materials used to form same High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a la... | 02/17/2004 |
| 6667196 | Method for real-time monitoring and controlling perovskite oxide film growth and semiconductor structure formed using the method High quality epitaxial layers of monocrystalline oxide materials (24) are grown overlying monocrystalline substrates such as large silicon wafers (22) using RHEED information to monitor the growth rate of the growing film. The monocrystalline oxide layer ... | 12/23/2003 |
| 6646293 | Structure for fabricating high electron mobility transistors utilizing the formation of complaint substrates High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a la... | 11/11/2003 |
| 6638872 | Integration of monocrystalline oxide devices with fully depleted CMOS on non-silicon substrates High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a la... | 10/28/2003 |
| 6635110 | Cyclic thermal anneal for dislocation reduction The invention provides processes for producing a very low dislocation density in heterogeneous epitaxial layers with a wide range of thicknesses, including a thickness compatible with conventional silicon CMOS processing. In a process for reducing disloca... | 10/21/2003 |
| 6589856 | Method and apparatus for controlling anti-phase domains in semiconductor structures and devices High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a la... | 07/08/2003 |
| 6472694 | Microprocessor structure having a compound semiconductor layer High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a la... | 10/29/2002 |
| 6472276 | Using silicate layers for composite semiconductor A composite semiconductor including silicon and compound semiconductor, and having a silicate layer for promoting layer-by-layer monocrystalline growth. Silicon may be introduced to react with the monocrystalline oxide layer to form the silicate layer. Du... | 10/29/2002 |
| 6352942 | Oxidation of silicon on germanium The invention provides processes for producing a high-quality silicon dioxide layer on a germanium layer. In one example process, a layer of silicon is deposited on the germanium layer, and the silicon layer is exposed to dry oxygen gas at a temperature t... | 03/05/2002 |
| 5495824 | Method for forming semiconductor thin film A method of forming a semiconductor thin film by crystallizing a thin film crystal from an amorphous thin film. A plurality of small regions which are preferentially made nuclei generation points are formed at predetermined positions in the amorphous thin... | 03/05/1996 |
| 5463975 | Process for producing crystal A process for producing a crystal comprises the step of applying crystal forming treatment on a light-transmissive substrate having a non-nucleation surface (SNDS) of a small nucleation density and a nucleation surface (SNDL) of a nu... | 11/07/1995 |
| 5395793 | Method of bandgap tuning of semiconductor quantum well structures A method of selectively tuning the bandedge of a semiconductor heterostructure includes repeatedly forming a disordered region that is spatially separated from a quantum well active region and subsequently annealing the heterostructure each time after the... | 03/07/1995 |
| 5391903 | Selective recrystallization to reduce P-channel transistor leakage in silicon-on-sapphire CMOS radiation hardened integrated circuits A silicon layer formed atop a sapphire substrate is selectively recrystallized such that the original degraded quality of the crystallinity of an N-well region where a P-channel device is to be formed is enhanced, so that leakage in the P-channel device i... | 02/21/1995 |
| 5360752 | Method to radiation harden the buried oxide in silicon-on-insulator structures A method of forming a radiation hardened SOI structure is disclosed. The buried oxide layer of an SOI structure is hardened prior to the bonding of a device wafer which forms the silicon portion of the silicon-on-insulator. The radiation hardening is done... | 11/01/1994 |
| 5298434 | Selective recrystallization to reduce P-channel transistor leakage in silicon-on-sapphire CMOS radiation hardened integrated circuits A preamorphized silicon layer formed atop a sapphire substrate is selectively recrystallized such that the original degraded quality of the crystallinity of an N-well region where a P-channel device is to be formed is enhanced, so that leakage in the P-ch... | 03/29/1994 |
| 5194395 | Method of producing a substrate having semiconductor-on-insulator structure with gettering sites A substrate has a semiconductor-on-insulator structure. The substrate has a base substrate, an insulator layer provided on the base substrate, an active substrate provided on the insulator layer and having gettering sites, and an active layer provided on ... | 03/16/1993 |
| 5063113 | Substrate having semiconductor-on-insulator structure with gettering sites and production method thereof A substrate has a semiconductor-on-insulator structure. The substrate has a base substrate, an insulator layer provided on the base substrate, an active substrate provided on the insulator layer and having gettering sites, and an active layer provided on ... | 11/05/1991 |
| 5059551 | Process for neutralizing acceptor atoms in p-type InP Process for neutralizing acceptor atoms in p-type InP. This process consists of subjecting to epitaxy a p-doped InP layer (4) and then a not intentionally doped Ga0.47 In0.53 As layer (6) on an InP semiinsulating substrate (2), followed b... | 10/22/1991 |
| 4863877 | Ion implantation and annealing of compound semiconductor layers A method for reducing the defect and dislocation density in III-V material layers deposited on dissimilar substrates is disclosed. The method involves ion implantation of dopant materials to create amorphous regions within the layers followed by an anneal... | 09/05/1989 |
| 4816893 | Low leakage CMOS/insulator substrate devices and method of forming the same A method of fabricating CMOS circuit devices on an insulator substrate is disclosed in which a solid phase epitaxy process is applied to islands for the individual devices in the same step as the channel dopant implants. An ion species, preferably silicon... | 03/28/1989 |
| 4753895 | Method of forming low leakage CMOS device on insulating substrate A method of fabricating CMOS circuit devices on an insulator substrate is disclosed in which a solid phase epitaxy process is applied to islands for the individual devices in the same step as the channel dopant implants. An ion species, preferably silicon... | 06/28/1988 |
| 4659392 | Selective area double epitaxial process for fabricating silicon-on-insulator structures for use with MOS devices and integrated circuits A process is disclosed for preparing selectively doped and recrystallized silicon-on-insulator semiconductor wafers, and wafers prepared thereby, wherein successive amorphizing and annealing sequences are utilized to optimize the defect structure and dopi... | 04/21/1987 |
| 4617066 | Process of making semiconductors having shallow, hyperabrupt doped regions by implantation and two step annealing A method for producing hyperabrupt P&#b1; or N&#b1; regions in a near-surface layer of a substantially defect free crystal, using solid phase epitaxy and transient annealing. The process for producing a hyperabrupt retrograde distribution of the dopant sp... | 10/14/1986 |
| 4588447 | Method of eliminating p-type electrical activity and increasing channel mobility of Si-implanted and recrystallized SOS films A silicon on sapphire (SOS) semiconductor structure may be processed to improve the electrical characteristics of a silicon film on a sapphire substrate by silicon-regrowth (SRG) techniques using oxidation to remove silicon from the outward surface of the... | 05/13/1986 |
| 4561916 | Method of growth of compound semiconductor A method for the growth of a compound semiconductor comprises growing on a silicon substrate a polycrystalline layer of a desired Group III-V compound semiconductor or a crystal layer of the desired Group III-V compound semiconductor having inferior cryst... | 12/31/1985 |
| 4509990 | Solid phase epitaxy and regrowth process with controlled defect density profiling for heteroepitaxial semiconductor on insulator composite substrates Disclosed is a method of fabricating a semiconductor on insulator composite substrate comprised of a semiconductor layer adjacent an insulator substrate, the defect density profile of the semiconductor layer being low and relatively uniform, a relatively ... | 04/09/1985 |
| 4463492 | Method of forming a semiconductor device on insulating substrate by selective amorphosization followed by simultaneous activation and reconversion to single crystal state A method for manufacturing a semiconductor device of a type in which a semiconductor element is formed on an insulating substrate. After ions which break the regularity of the crystal lattice of a monocrystalline semiconductor layer formed on the insulati... | 08/07/1984 |
| 4404265 | Epitaxial composite and method of making An epitaxial composite comprising a thin film of single crystal Group III-V wide band-gap compound semiconductor or semiconductor alloy on single crystal, electrically insulating oxide substrates such as sapphire, spinel, BeO, ThO2, or the like... | 09/13/1983 |
| 4385937 | Regrowing selectively formed ion amorphosized regions by thermal gradient Processes for forming a wafer having SOS structure are provided. A single crystal silicon layer is formed on a principal plane of a sapphire substrate. An amorphous portion is formed in a silicon layer leaving its surface portion of predetermined depth as... | 05/31/1983 |
| 4373254 | Method of fabricating buried contacts A novel method for forming a buried contact wherein the area of the buried contact is preconditioned by being doped to thus preclude the formation of an undesirable junction surrounding the buried contact.... | 02/15/1983 |
