Class 257/E21.103 - Deposition on a semiconductor substrate which is different from the semiconductor material being deposited, i.e., formation of heterojunctions (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.102. This subclass
No. of patents: 21
Last issue date: 10/21/2008

Number	Title	Issue Date
7439567	Contactless nonvolatile memory array An array of memory cells with non-volatile memory transistors having a compact arrangement of diagonally symmetric floating gates. The floating gates have portions extending in both X and Y directions, allowing them to be charged through a common tunnel oxide stripe...	10/21/2008
7429766	Split gate type nonvolatile memory device In a split gate type nonvolatile memory device, a supplementary layer pattern is disposed on a source region of a semiconductor substrate. Since the source region is vertically extended by virtue of the presence of the supplementary layer pattern, it is therefore po...	09/30/2008
7399686	Method and apparatus for making coplanar dielectrically-isolated regions of different semiconductor materials on a substrate A semiconductor processing method includes providing a substrate, forming a plurality of semiconductor layers in the substrate, each of the semiconductor layers being distinct and selected from different groups of semiconductor element types, the semiconductor layer...	07/15/2008
7365383	Method of forming an EPROM cell and structure therefor An EPROM cell includes a control gate and a control transistor. A portion of the control transistor is formed as a portion of the control gate. ...	04/29/2008
7341929	Method to fabricate patterned strain-relaxed SiGe epitaxial with threading dislocation density control A method to fabricate patterned strain-relaxed SiGe epitaxial with threading dislocation density control is provided. An ion-implanting area is first defined on a silicon substrate, and then proceeds ion-implanting. Finally, a buffer layer and a SiGe epitaxial layer...	03/11/2008
7339226	Dual-level stacked flash memory cell with a MOSFET storage transistor The present invention is a dual-level flash memory cell design that stores 3 or more bits of information per transistor. The dual-level memory cell stores two lower bits in a first level and stores an upper bit in a second level. The lower bits are programmed, erase...	03/04/2008
7332399	Method for manufacturing a semiconductor substrate and method for manufacturing a semiconductor in which film thicknesses can be accurately controlled A method of manufacturing semiconductor substrates. After supporting layers are provided on side walls of grooves formed in a semiconductor substrate, grooves that expose a second semiconductor layer are formed. Etching gas or etching liquid is brought in contact wi...	02/19/2008
7312136	Method of fabricating a wafer with strained channel layers for increased electron and hole mobility for improving device performance A method for making a SOI wafer with a strained silicon layer for increased electron and hole mobility is achieved. The method forms a porous silicon layer on a seed wafer. A H2 anneal is used to form a smooth surface on the porous silicon. A strain free ...	12/25/2007
7294883	Nonvolatile memory cells with buried channel transistors In a nonvolatile memory cell (110), the select gate transistor is formed as a buried channel transistor to increase the transistor current. ...	11/13/2007
7262117	Germanium integrated CMOS wafer and method for manufacturing the same The present invention discloses an integration flow of germanium into a conventional CMOS process, with improvements in performing selective area growth, and implementing electrical contacts to the germanium, in a way that has minimal impact on the preexisting trans...	08/28/2007
7229901	Fabrication of strained heterojunction structures Growth of multilayer films is carried out in a manner which allows close control of the strain in the grown layers and complete release of the grown films to allow mounting of the released multilayer structures on selected substrates. A layer of material, such as si...	06/12/2007
6528394	Growth method of gallium nitride film A method of growing a high quality gallium nitride (GaN) film at a high growth rate, which is used in homoepitaxy blue laser diodes or electronic devices. In the GaN film growth method, a bare sapphire substrate is nitridated in a reactor, and then sequen...	03/04/2003
6228166	Method for boron contamination reduction in IC fabrication In order to reduce boron concentration between a silicon substrate and an Si or Si1-x Gex layer which is epitaxially grown in a CVD (chemical vapor deposition) apparatus, the silicon substrate is pretreated, before being loaded into ...	05/08/2001
5670414	Graded-gap process for growing a SiC/Si heterojunction structure The present invention relates to a graded-gap process for forming a SiC/Si heterojunction electrical element and includes steps of a) provide a Si substrate; b) introduce a hydrogen containing gas stream to the Si substrate; c) introduce a silane-containi...	09/23/1997
5256550	Fabricating a semiconductor device with strained Si_1-x Ge_x layer The present invention comprises a method of fabricating devices and circuits employing at least one heteroepitaxial layer under strain. The thickness of the heteroepitaxial layer is more than two times the calculated equilibrium critical thickness for an ...	10/26/1993
5091333	Reducing dislocations in semiconductors utilizing repeated thermal cycling during multistage epitaxial growth Dislocation densities are reduced in growing semiconductors from the vapor phase by employing a technique of interrupting growth, cooling the layer so far deposited, and then repeating the process until a high quality active top layer is achieved. The met...	02/25/1992
5084411	Semiconductor processing with silicon cap over Si_1-x Ge_x Film Improved devices with silicon to SiGe alloy heterojunctions are provided for in accordance with the following discoveries. X-ray topography and transmission electron microscopy were used to quantify misfit-dislocation spacings in as-grown Si1-x...	01/28/1992
4885614	Semiconductor device with crystalline silicon-germanium-carbon alloy The present invention discloses a semiconductor device comprising a semiconductor layer being made of monocrystalline silicon or silicon-germanium alloy and a semiconductor layer being made of silicon-germanium-carbon alloy formed thereon, wherein the two...	12/05/1989
4843030	Semiconductor processing by a combination of photolytic, pyrolytic and catalytic processes A semiconductor processing method is provided for growing a semiconductor film from a semiconductorbearing gas on a substrate at a substrate temperature below the pyrolytic threshold of the gas. The gas is photodissociated to a collisionally stable specie...	06/27/1989
4632712	Reducing dislocations in semiconductors utilizing repeated thermal cycling during multistage epitaxial growth Dislocation densities are reduced in growing semiconductors from the vapor phase by employing a technique of interrupting growth, cooling the layer so far deposited, and then repeating the process until a high quality active top layer is achieved. The met...	12/30/1986
4357183	Heteroepitaxy of germanium silicon on silicon utilizing alloying control A method and apparatus is described for producing Ge or a Ge1-x Six heteroepitaxy film on Si by depositing films of Ge or Ge1-x Six on Si and subjecting the body so formed to a controlled temperature environment...	11/02/1982

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Class 257/E21.103 - Deposition on a semiconductor substrate which is different from the semiconductor material being deposited, i.e., formation of heterojunctions (EPO)