Class 257/E21.092 - Epitaxial deposition of Group IV element, e.g., Si, Ge (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.091. This subclass
No. of patents: 57
Last issue date: 10/28/2008

«First «Previous1 2 Next»Last»

Number	Title	Issue Date
7442657	Producing stress-relaxed crystalline layer on a substrate A stress relaxed monocrystalline layer structure is made on a nonlattice matched substrate by first applying to the substrate epitaxially a monocrystalline layer structure comprising at least one layer, the monocrystalline layer structure forming with the substrate ...	10/28/2008
7419891	Method and system for providing a smaller critical dimension magnetic element utilizing a single layer mask The method and system for providing a magnetic element are disclosed. The method and system include providing a magnetic element stack that includes a plurality of layers and depositing a stop layer on the magnetic element stack. The method and system also include p...	09/02/2008
7416909	Methods for preserving strained semiconductor substrate layers during CMOS processing Oxidation methods, which avoid consuming undesirably large amounts of surface material in Si/SiGe heterostructure-based wafers, replace various intermediate CMOS thermal oxidation steps. First, by using oxide deposition methods, arbitrarily thick oxides may be forme...	08/26/2008
7393762	Charge-free low-temperature method of forming thin film-based nanoscale materials and structures on a substrate A method of forming a nanostructure at low temperatures. A substrate that is reactive with one of atomic oxygen and nitrogen is provided. A flux of neutral atoms of at least one of nitrogen and oxygen is generated within a laser-sustained-discharge plasma source and...	07/01/2008
7387925	Integration of strained Ge into advanced CMOS technology A structure and method of fabrication for PFET devices in a compressively strained Ge layer is disclosed. The fabrication method of such devices is compatible with standard CMOS technology and it is fully scalable. The processing includes selective epitaxial deposit...	06/17/2008
7384837	Method for isolating silicon germanium dislocation regions in strained-silicon CMOS applications A dual gate strained-Si MOSFET with thin SiGe dislocation regions and a method for fabricating the same are provided. The method forms a first layer of relaxed SiGe overlying a substrate, having a thickness of less than 5000 Å; forms a second layer of relaxed SiGe...	06/10/2008
7371665	Method for fabricating shallow trench isolation layer of semiconductor device A method for fabricating an STI layer of a semiconductor device is disclosed, to improve the integration of the semiconductor device in a method of increasing a moat area for a gate line by minimizing an isolation area between moat areas, which includes the steps of...	05/13/2008
7361528	Germanium infrared sensor for CMOS imagers A method of fabricating a germanium infrared sensor for a CMOS imager includes preparation of a donor wafer, including: ion implantation into a silicon wafer to form a P+ silicon layer; growing an epitaxial germanium layer on the P+silicon layer, forming a silicon-g...	04/22/2008
7354835	Method of fabricating CMOS transistor and CMOS transistor fabricated thereby In a method of fabricating a CMOS transistor, and a CMOS transistor fabricated according to the method, the characteristics of first and second conductivity type MOS transistors are both simultaneously improved. At the same time, the fabrication process is simplifie...	04/08/2008
7348229	Method of manufacturing a semiconductor device and semiconductor device obtained with such a method The invention relates to a method of manufacturing a semiconductor device (10) with a field effect transistor, in which method a semiconductor body (1) of silicon is provided at a surface thereof with a source region (2) and a drain region (3...	03/25/2008
7344933	Method of forming device having a raised extension region A method is disclosed of forming an extension region for a transistor having a gate structure overlying a compound semiconductor layer. An anneal is used either before or after deep source/drain implantation to diffuse a dopant from a raised region adjacent the gate...	03/18/2008
7341883	Silicon germanium semiconductive alloy and method of fabricating same A silicon germanium (SiGe) semiconductive alloy is grown on a substrate of single crystalline Al2O3. A {111} crystal plane of a cubic diamond structure SiGe is grown on the substrate's {0001} C-plane such that a orientation of the cubic d...	03/11/2008
7338886	Implantation-less approach to fabricating strained semiconductor on isolation wafers A method of fabricating a semiconductor substrate includes forming a buffer layer on the substrate. A Ge containing layer, such as a SiGe is formed over the buffer layer. The buffer layer includes defects at the interface of the substrate and buffer layer. The subst...	03/04/2008
7329596	Method for tuning epitaxial growth by interfacial doping and structure including same A method that allows for uniform, simultaneous epitaxial growth of a semiconductor material on dissimilarly doped semiconductor surfaces (n-type and p-type) that does not impart substrate thinning via a novel surface preparation scheme, as well as a structure that r...	02/12/2008
7288430	Method of fabricating heteroepitaxial microstructures An efficient method of fabricating a high-quality heteroepitaxial microstructure having a smooth surface. The method includes detaching a layer from a base structure to provide a carrier substrate having a detached surface, and then forming a heteroepitaxial microst...	10/30/2007
7279369	Germanium on insulator fabrication via epitaxial germanium bonding A method of forming a germanium-on-insulator (GOI). An epitaxial germanium layer is formed on top of a first substrate. A first dielectric film is formed on top of the epitaxial germanium layer. A second substrate is provided. The first substrate is bonded to the se...	10/09/2007
7273818	Film formation method and apparatus for semiconductor process In a film-formation method for a semiconductor process, a silicon germanium film is formed on a target substrate by CVD in a process field within a reaction container. Then, a silicon coating film is formed to cover the silicon germanium film by CVD in the process f...	09/25/2007
7268027	Method of manufacturing photoreceiver Disclosed is a method of manufacturing a photoreceiver, including sequentially laminating a buffer layer, a channel layer, a barrier layer, and a cap layer on a substrate; forming a mesa for HEMT and MSM PD by removing the buffer layer, the channel layer, the barrie...	09/11/2007
7247896	Semiconductor devices having a field effect transistor and methods of fabricating the same A semiconductor device having a field effect transistor and a method of forming the same are provided. The semiconductor device preferably includes a device active pattern disposed on a predetermined region of the substrate. The gate electrode preferably crosses ove...	07/24/2007
7244654	Drive current improvement from recessed SiGe incorporation close to gate A method (100) of forming a transistor includes forming a gate structure (106, 108) over a semiconductor body and forming recesses (112) substantially aligned to the gate structure in the semiconductor body. Silicon germanium is then epitaxially...	07/17/2007
7208362	Transistor device containing carbon doped silicon in a recess next to MDD to create strain in channel A method (100) of forming a transistor includes forming a gate structure (106, 108) over a semiconductor body and forming recesses (112) substantially aligned to the gate structure in the semiconductor body. Carbon-doped silicon is then epitaxia...	04/24/2007
7202121	Methods for preserving strained semiconductor substrate layers during CMOS processing Oxidation methods, which avoid consuming undesirably large amounts of surface material in Si/SiGe heterostructure-based wafers, replace various intermediate CMOS thermal oxidation steps. First, by using oxide deposition methods, arbitrarily thick oxides may be forme...	04/10/2007
7199011	Method to reduce transistor gate to source/drain overlap capacitance by incorporation of carbon The present invention pertains to formation of a transistor in a manner that mitigates overlap capacitances, thereby facilitating, among other things, enhanced switching speeds. More particularly, a gate stack of the transistor is formed to include an optional layer...	04/03/2007
7183168	Method of manufacturing a semiconductor device having a silicide film A method of manufacturing a semiconductor device includes implanting germanium ions into a selected portion of a semiconductor region containing at least silicon, forming P-type and N-type diffusion layers in the semiconductor region, and forming a suicide film whic...	02/27/2007
7119032	Method to protect internal components of semiconductor processing equipment using layered superlattice materials This invention relates to apparatus and a method to protect the internal components of semiconductor processing equipment such as a plasma reactor or a reactive species generator against physical and/or chemical damages during etching and/or cleaning processes. Laye...	10/10/2006
6649032	System and method for sputtering silicon films using hydrogen gas mixtures A method has been provided for forming a polycrystalline silicon (p-Si) film with a small amount of hydrogen. Such a film has been found to have excellent sheet resistance, and it is useful in the fabrication of liquid crystal display (LCD) panels made fr...	11/18/2003
6350311	Method for forming an epitaxial silicon-germanium layer A method for growing an epitaxial silicon-germanium layer is described. The method includes removing a native oxide layer on the silicon substrate surface. A HF vapor treatment process is then conducted on the silicon substrate. Thereafter, a germanium la...	02/26/2002
6344116	Monocrystalline three-dimensional integrated-circuit technology Three technologies realize monocrystalline three-dimensional (3-D) integrated circuits: (1) silicon sputter epitaxy permitting fast growth at low temperature; (2) real-time pattern generation using a pixel-by-pixel programmable device to create a patterne...	02/05/2002
5937318	Monocrystalline three-dimensional integrated circuit A monocrystalline monolith contains a 3-D array of interconnected lattice-matched devices (which may be of one kind exclusively, or that kind in combination with one or more other kinds) performing digital, analog, image-processing, or neural-network func...	08/10/1999
5854495	Preparation of nucleated silicon surfaces A structure is disclosed for growing semiconductor surfaces. A substrate such as a single crystal silicon substrate is treated by electrical biasing in the presence of a carbon-containing plasma to cause nucleation of the surface. By direct observation us...	12/29/1998
5840589	Method for fabricating monolithic and monocrystalline all-semiconductor three-dimensional integrated circuits A method is described for growing a single crystal having three-dimensional (3-D) doping patterns created within it during growth while maintaining a plane growth surface, creating junction-isolated devices and interconnections, forming a 3-D integrated c...	11/24/1998
5560777	Apparatus for making a semiconductor An apparatus for making a semiconductor at atmospheric pressure having a first electrode and second electrode which are adapted to receive an RF voltage to perform corona discharge, the first electrode and second electrode together forming a corona discha...	10/01/1996
5510011	Method for forming a functional deposited film by bias sputtering process at a relatively low substrate temperature In a bias sputtering method comprising generating a plasma of a sputtering gas between a target electrode having a target thereon and a substrate electrode having a substrate for film formation thereon in a vacuum vessel with the use of a high frequency e...	04/23/1996
5424103	Method for making a semiconductor using corona discharge A method for making a semiconductor, without using a vacuum pump or vacuum chamber, using corona discharge, which comprises the steps or: supplying a reactive gas to, at least, one electrode capable of generating corona discharge above a substrate with an...	06/13/1995
5374846	Bipolar transistor with a particular base and collector regions A silicon film 9 and an N+ -type impurity region 9a are provided between a base region 11 and an epitaxial growth layer 3. A silicon oxide film 12 is provided on the inner sidewalls of an opening 16, and an N-type polycrystalline silicon film 1...	12/20/1994
5254237	Plasma arc apparatus for producing diamond semiconductor devices A diamond deposition system and process for producing diamond semiconductor devices. A multiple gun plasma arc deposition system allows controlled deposition of diamond-like materials on a substrate. Deposition is controlled by controlling the time durati...	10/19/1993
5169798	Forming a semiconductor layer using molecular beam epitaxy Disclosed is a method of making a semiconductor device that comprises MBE at substrate temperatures substantially lower than conventionally used temperatures. A significant aspect of the method is the ability to produce highly doped (e.g., 1019...	12/08/1992
4949146	Structured semiconductor body A structured semiconductor body e.g., an integrated circuit or a transistor, based on an silicon substrate having barrier regions which contain polycrystalline silicon, preferably produced by a silicon MBE process. The barrier regions are required to deli...	08/14/1990
4935375	Method of making a semiconductor device A structured semiconductor body based on a Si substrate and having monocrystalline semiconductor regions and barrier regions which contain polycrystalline silicon which have preferably been produced in an Si-MBE process. The barrier regions are provided t...	06/19/1990
4912538	Structured semiconductor body A structured semiconductor body based on a Si substrate and having monocrystalline semiconductor regions and barrier regions which contain polycrystalline silicon which have preferably been produced in an Si-MBE process. The barrier regions are provided t...	03/27/1990

«First «Previous1 2 Next»Last»

PatentStorm

Bizarre Patents

PatentStorm News

Class 257/E21.092 - Epitaxial deposition of Group IV element, e.g., Si, Ge (EPO)