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| Number | Title | Issue Date |
| 7439175 | Method for fabricating a thin film and metal line of semiconductor device A method for forming a thin film of a semiconductor device is provided. The method includes forming a TaN film on a semiconductor substrate, and converting a portion of the TaN film into a Ta film by reacting the TaN film with NO2. The Ta film is formed t... | 10/21/2008 |
| 7432193 | Method for fabricating a thin film and a metal line of a semiconductor device A method for forming a thin film of a semiconductor device is provided. The method includes forming a TaN film on a semiconductor substrate by employing an atomic layer deposition method; and converting a part of the TaN film into a Ta by reacting the TaN film with ... | 10/07/2008 |
| 7348226 | Method of forming lattice-matched structure on silicon and structure formed thereby A method (and resultant structure) of forming a semiconductor structure, includes processing an oxide to have a crystalline arrangement, and depositing an amorphous semiconductor layer on the oxide by one of evaporation and chemical vapor deposition (CVD). ... | 03/25/2008 |
| 7339249 | Semiconductor device An insulating film is provided in a region surrounding a circuit region on a p type silicon substrate, and a frame-shaped electrode is provided to surround the circuit region on the insulating film. The region directly under the electrode at the surface of the p typ... | 03/04/2008 |
| 7294526 | Nano optical sensors via molecular self-assembly An optical sensor is provided, comprising (a) a silicon nanowire of finite length having an electrical contact pad at each end thereof; and (b) a plurality of self-assembled molecules on a surface of the silicon nanowire, the molecules serving to modulate electrical... | 11/13/2007 |
| 7214575 | Method and apparatus providing CMOS imager device pixel with transistor having lower threshold voltage than other imager device transistors A transistor of a pixel cell for use in a CMOS imager with a low threshold voltage of about 0.3 V to less than about 0.7 V is disclosed. The transistor is provided with high dosage source and drain regions around the gate electrode and with the halo implanted region... | 05/08/2007 |
| 7205662 | Dielectric barrier layer films In accordance with the present invention, a dielectric barrier layer is presented. A barrier layer according to the present invention includes a densified amorphous dielectric layer deposited on a substrate by pulsed-DC, substrate biased physical vapor deposition, w... | 04/17/2007 |
| 7190016 | Capacitor structure Structures including a capacitor dielectric material disposed on the surface of an electrode suitable for use in forming capacitors are disclosed. Methods of forming such structures are also disclosed. ... | 03/13/2007 |
| 7179696 | Phosphorus activated NMOS using SiC process A method (10) of forming a transistor (100) includes treating (12) at least some of a semiconductor substrate (102) with carbon and then forming (18) a gate structure (114) over the semiconductor substrate. A channel region ... | 02/20/2007 |
| 7161220 | High speed photodiode with a barrier layer for blocking or eliminating slow photonic carriers and method for forming same A structure (and method for forming the structure) includes a photodetector, a substrate formed under the photodetector, and a barrier layer formed over the substrate. The buried barrier layer preferably includes a single or dual p-n junction, or a bubble layer for ... | 01/09/2007 |
| 7129580 | Methods and procedures for engineering of composite conductive films by atomic layer deposition A composite film comprised of three layers is formed by ALD on a substrate with a substrate interface surface. A first layer is coupled to the substrate interface surface. The first layer provides adhesion to the substrate interface surface and initiation of layer b... | 10/31/2006 |
| 5543335 | Advanced power device process for low drop A method for fabricating a power semiconductor device with a low forward voltage drop using polymer passivation. A polymer passivation layer is deposited over the device. Impurities are introduced into the backside of the device by ion implantation, the b... | 08/06/1996 |
