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| Number | Title | Issue Date |
| 7396781 | Method and apparatus for adjusting feature size and position Variations in the pitch of features formed using pitch multiplication are minimized by separately forming at least two sets of spacers. Mandrels are formed and the positions of their sidewalls are measured. A first set of spacers is formed on the sideswalls. The cri... | 07/08/2008 |
| 7381654 | Method for fabricating right-angle holes in a substrate A method is disclosed for forming right-angle contact/via holes for semiconductor devices. A device is provided on a substrate and covered with a first dielectric layer. A second dielectric layer having an etch rate different from that of the first layer is provided... | 06/03/2008 |
| 7361588 | Etch process for CD reduction of arc material A method of reducing critical dimensions of a feature in a anti-reflective coating layer structure can utilize a polymerizing agent. The anti-reflective coating structure can be utilized to form various integrated circuit structures. The anti-reflective coating can ... | 04/22/2008 |
| 7351666 | Layout and process to contact sub-lithographic structures An integrated circuit and method for fabrication includes first and second structures, each including a set of sub-lithographic lines, and contact landing segments connected to at least one of the sub-lithographic lines at an end portion. The first and second struct... | 04/01/2008 |
| 7316978 | Method for forming recesses A method for forming a recess. The method includes providing a substrate with two protrusions having a first side wall and a second side wall opposite to the first side wall disposed above the substrate, conformally forming a mask layer on the substrate and the prot... | 01/08/2008 |
| 7314824 | Nitrogen-free ARC/capping layer and method of manufacturing the same The present invention provides a nitrogen-free ARC/capping layer in a low-k layer stack, which, in particular embodiments, is comprised of carbon-containing silicon dioxide, wherein the optical characteristics are tuned to conform to the 193 nm lithography. Moreover... | 01/01/2008 |
| 7179748 | Method for forming recesses A method for forming a recess. The method includes providing a substrate with two protrusions having a first side wall and a second side wall opposite to the first side wall disposed above the substrate, conformally forming a mask layer on the substrate and the prot... | 02/20/2007 |
| 6699792 | Polymer spacers for creating small geometry space and method of manufacture thereof In forming an opening or space in a substrate, a layer of photoresist is provided on the substrate, and the photoresist is patterned to provide photoresist bodies having respective adjacent sidewalls. A polymer layer is provided on the resulting structure... | 03/02/2004 |
| 6673714 | Method of fabricating a sub-lithographic sized via A method of fabricating a sub-lithographic sized via is disclosed. A dual-polymer method is used to form a stacked layer of polymer materials wherein a first polymer layer has a first etch rate and a second polymer layer has a second etch rate. The first ... | 01/06/2004 |
| 6670277 | Method of manufacturing semiconductor device A semiconductor device manufacturing method for manufacturing a semiconductor device of constant finished dimensions as designed even when a material which is difficult to increase etch selectivity to a silicon film in a gate electrode or wiring structure... | 12/30/2003 |
| 6667237 | Method and apparatus for patterning fine dimensions A process of forming fine repetitive geometries using a mask having large mask dimensions. The pitch of the masking pattern on the mask is divided by the process to obtain a smaller pitch in the fine repetitive geometries. At least two working materials a... | 12/23/2003 |
| 6664191 | Non self-aligned shallow trench isolation process with disposable space to define sub-lithographic poly space A method is provided of forming lines with spaces between memory cells below a minimum printing dimension of a photolithographic tool set. In one aspect of the invention, lines and spaces are formed in a first polysilicon layer that forms floating gates o... | 12/16/2003 |
| 6653058 | Methods for reducing profile variation in photoresist trimming A method of removing photoresist material from a semiconductor substrate includes providing a semiconductor substrate having a patterned photoresist mask. A layer comprised of polymer material is formed over the patterned photoresist mask. The layer compr... | 11/25/2003 |
| 6642152 | Method for ultra thin resist linewidth reduction using implantation The present invention relates to a system and a method for reducing the linewidth of ultra thin resist features. The present invention accomplishes this end by applying a densification process to an ultra thin resist having a thickness of less than about ... | 11/04/2003 |
| 6638441 | Method for pitch reduction A method for pitch reduction is disclosed. The method can form a pattern with a pitch 1/3 the original pitch formed by available photolithography technologies by only using one photo mask or one pattern transfer process, self-aligned etching back processe... | 10/28/2003 |
| 6620715 | Method for forming sub-critical dimension structures in an integrated circuit A method is provided for fabricating a device, which includes device components and spacings that may each have a final dimension that is smaller than a minimum dimension obtainable by a photolithography process used to form the device components. In part... | 09/16/2003 |
| 6617085 | Wet etch reduction of gate widths A method of forming sublithography gate lengths involves the steps of patterning the layer of resist above the gate stack (including a gate layer, hardmask layer and etch-control layer) to a desired gate length and etching the etch-control layer and the h... | 09/09/2003 |
| 6610607 | Method to define and tailor process limited lithographic features using a modified hard mask process A method to define and tailor process limited lithographic features is provided. The method may be used to form sub lithographic spaces between features on a semiconductor wafer. A mask is formed and patterned on the wafer. Spacers are formed on sidewalls... | 08/26/2003 |
| 6605541 | Pitch reduction using a set of offset masks A method of manufacturing a semiconductor device having features with a dimension of 1/2the minimum pitch wherein the minimum pitch is determined by the parameters of the manufacturing process being used to manufacture the semiconductor device. A target l... | 08/12/2003 |
| 6570220 | Fabrication of deep submicron structures and quantum wire transistors using hard-mask transistor width definition The invention relates to a method of forming reduced feature size spacers. The method includes providing a semiconductor substrate having an area region; patterning a first spacer over a portion of the area region of the substrate, the first spacer having... | 05/27/2003 |
| 6566280 | Forming polymer features on a substrate Polymer features may be formed on a substrate by applying a polymer to a photoresist pattern which is subsequently removed to generate the desired polymer features.... | 05/20/2003 |
| 6548385 | Method for reducing pitch between conductive features, and structure formed using the method A method is described which may be used to reduce a pitch between conductive features. One embodiment of the method involves forming a structure including a substrate, a conductive layer on the substrate, multiple photoresist features arranged on the cond... | 04/15/2003 |
| 6541360 | Bi-layer trim etch process to form integrated circuit gate structures A bi-layer trim etch process to form integrated circuit gate structures can include depositing an organic underlayer over a layer of polysilicon, depositing an imaging layer over the organic underlayer, patterning the imaging layer, selectively trim etchi... | 04/01/2003 |
| 6525353 | Anti-reflection structure for a conductive layer in a semiconductor device An anti-reflection structure formed on a gate electrode in a MOSFET device includes a first and second anti-reflection layers sandwiching therebetween a silicon nitride layer. Each of the anti-reflection layers has a two-layer structure including a silico... | 02/25/2003 |
| 6524945 | Method of making an anti-reflection structure for a conductive layer in a semiconductor device An anti-reflection structure formed on a gate electrode in a MOSFET device includes a first and second anti-reflection layers sandwiching therebetween a silicon nitride layer. Each of the anti-reflection layers has a two-layer structure including a silico... | 02/25/2003 |
| 6489237 | Method of patterning lines in semiconductor devices A new process is provided for the creation of sub-micron conductive lines and patterns. A conductive layer is deposited over the surface of a substrate, a sacrificial layer that differs with the conductive layer in etch characteristics is deposited over t... | 12/03/2002 |
| 6479861 | Method for forming an etch mask during the manufacture of a semiconductor device A method used during the formation of a semiconductor device comprises the steps of forming a polycrystalline silicon layer over a semiconductor substrate assembly and forming a silicon nitride layer over the polycrystalline silicon layer. A silicon dioxi... | 11/12/2002 |
| 6475867 | Method of forming integrated circuit features by oxidation of titanium hard mask An exemplary method of forming integrated circuit device features by oxidization of titanium hard mask is described. This method can include providing a photoresist pattern of photoresist features over a first layer of material deposited over a second lay... | 11/05/2002 |
| 6429123 | Method of manufacturing buried metal lines having ultra fine features The present invention provides a method for manufacturing a plurality of buried metal lines on a semiconductor substrate. The method comprises the steps as below. A dielectric layer is formed on a semiconductor substrate. And a plurality of insulator bloc... | 08/06/2002 |
| 6383853 | Method of fabricating semiconductor device A method of fabricating a semiconductor device, capable of forming a pattern more finely and more variously without depending on the performance of an exposing device. Aluminum is vapor deposited on a spacer film from an oblique direction to form a metal ... | 05/07/2002 |
| 6329124 | Method to produce high density memory cells and small spaces by using nitride spacer The present invention relates to a method for forming an etch mask. A photoresist layer is patterned, wherein d1 is a smallest space dimension of an exposed area of a layer underlying the photoresist layer. An ARC layer under the photoresist la... | 12/11/2001 |
| 6140194 | Method relating to the manufacture of a semiconductor component A manufacturing method for semiconductor components is disclosed which will allow better precision in the definition of the doped areas of the components and the separation of differently doped areas. A selectively shaped area of, for example, polysilicon... | 10/31/2000 |
| 6124167 | Method for forming an etch mask during the manufacture of a semiconductor device A method used during the formation of a semiconductor device comprises the steps of forming a polycrystalline silicon layer over a semiconductor substrate assembly and forming a silicon nitride layer over the polycrystalline silicon layer. A silicon dioxi... | 09/26/2000 |
| 6110837 | Method for forming a hard mask of half critical dimension The present invention discloses a method for forming hard mask of half critical dimension on a substrate. A substrate is provided for the base of integrated circuits. A silicon oxide layer is formed on the substrate. A photoresist layer is formed on the s... | 08/29/2000 |
| 6096659 | Manufacturing process for reducing feature dimensions in a semiconductor A process for reducing dimensions of circuit elements in a semiconductor device. The process reduces feature sizes by using an intermediate etchable mask layer between a photo-resistive mask and a layer to be etched. The etchable mask layer below the phot... | 08/01/2000 |
| 6063688 | Fabrication of deep submicron structures and quantum wire transistors using hard-mask transistor width definition The invention relates to a method of forming reduced feature size spacers. The method includes providing a semiconductor substrate having an area region; patterning a first spacer over a portion of the area region of the substrate, the first spacer having... | 05/16/2000 |
| 6060377 | Method for fabricating a polysilicon structure with reduced length that is beyond photolithography limitations A polysilicon structure is fabricated with a reduced length that is beyond that achievable from photolithography by using a silicidation anneal to control the reduced length. Generally, the present invention includes a step of forming a masking polysilico... | 05/09/2000 |
| 6040214 | Method for making field effect transistors having sub-lithographic gates with vertical side walls A method for the formation of field effect transistors (FETs), and more particularly metal oxide field effect transistors (MOSFETs), comprising the steps of: forming a dielectric stack on a semiconductor structure; defining an etch window on the dielectri... | 03/21/2000 |
| 6036875 | Method for manufacturing a semiconductor device with ultra-fine line geometry A method for ultra-fine patterning of a semiconductor device performs a first, anisotropic etching of a hard mask layer according to a pattern created by lithographic techniques to create lines in the hard mask layer having an initial width. A second, ani... | 03/14/2000 |
| 6027972 | Method for producing very small structural widths on a semiconductor substrate Very narrow structures are produced on a semiconductor substrate. A first layer deposited over an edge of a structure is anisotropically etched back. The spacer at the edge of the structure which remains after the first layer and the structure are removed... | 02/22/2000 |
