Class 257/E21.034 - For lift-off process (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.033. This subclass
No. of patents: 37
Last issue date: 11/06/2007

Number	Title	Issue Date
7291891	In-solid nuclear spin quantum calculation device A voltage is applied across gate electrodes (103A) and (103B) in a two-dimensional electronic system (101) placed under a magnetic field, and the polarity of an electric current passed between ohmic electrodes (102D) and (102S) is ...	11/06/2007
7008810	Method for fabricating at least one mesa or ridge structure or at least one electrically pumped region in a layer or layer sequence A method for fabricating at least one mesa or ridge structure in a layer or layer sequence, in which a sacrificial layer (4) is applied and patterned above the layer or layer sequence. A mask layer is applied and patterned above the sacrificial layer for defi...	03/07/2006
6627526	Method for fabricating a conductive structure for a semiconductor device A process for making semiconductor structures, and the resulting highly conductive semiconductor structures, includes using damascene process to form a structure with a thin adhesive layer and overlaying conductive layer. The highly conductive semiconduct...	09/30/2003
6623988	Method for fabricating ferroelectric capacitor of semiconductor device A method for fabricating a ferroelectric capacitor of a semiconductor device is disclosed. This method carries out a patterning process of a capacitor electrode, which is difficult to handle in a dry etching process, with a lift-off method using a negativ...	09/23/2003
6590250	DRAM capacitor array and integrated device array of substantially identically shaped devices Semiconductor processing methods include forming a plurality of patterned device outlines over a semiconductor substrate, forming electrically insulative partitions or spacers on at least a portion of the patterned device outlines, and forming a plurality...	07/08/2003
6451684	Semiconductor device having a conductive layer side surface slope which is at least 90° and method for manufacturing the same A semiconductor device having a conductive layer side surface slope of at least 90° and a method for making the same is provided. An interlayer dielectric film and a conductive layer are formed on a semiconductor substrate. The interlayer dielectric film...	09/17/2002
6383853	Method of fabricating semiconductor device A method of fabricating a semiconductor device, capable of forming a pattern more finely and more variously without depending on the performance of an exposing device. Aluminum is vapor deposited on a spacer film from an oblique direction to form a metal ...	05/07/2002
6365470	Method for manufacturing self-matching transistor A diffusion source included a diffusion source layer is diffused into both a source area and a drain area in a self-aligning manner by using heat treatment, and after the self-aligning thermal diffusion, a gate insulating film and a metal gate electrode a...	04/02/2002
6156665	Trilayer lift-off process for semiconductor device metallization The specification describes a trilevel resist technique for defining metallization patterns by lift-off. The trilevel resist comprises two standard photoresist levels separated by a thin silicon oxide layer with approximate composition SiO2....	12/05/2000
6121653	Dram capacitor arrays with 3-capacitor and 6-capacitor geometries Semiconductor processing methods include forming a plurality of patterned device outlines over a semiconductor substrate, forming electrically insulative partitions or spacers on at least a portion of the patterned device outlines, and forming a plurality...	09/19/2000
6080514	Fabrication method of mask for semiconductor device A fabrication method of a mask for a semiconductor device includes the steps of: applying a first photoresist film on a silicone wafer; sequentially stacking a first insulation film, a second insulation film, and a second photoresist film on the first pho...	06/27/2000
6048671	Ultra-fine microfabrication method using an energy beam An ultra-fine microfabrication method using an energy beam is based on the use of shielding provided by nanometer or micrometer sized micro-particles to produce a variety of three-dimensional fine structures which have not been possible by the traditional...	04/11/2000
6015976	Fabrication apparatus employing energy beam Three-dimensional ultra-fine micro-fabricated structures of the order of μm and less are produced for use in advanced optical communication systems and quantum effect devices. Basic components are an energy beam source, a mask member and a specimen stage...	01/18/2000
6010831	Ultra-fine microfabrication method using an energy beam An ultra-fine microfabrication method using an energy beam is based on the use of shielding provided by nanometer or micrometer sized micro-particles to produce a variety of three-dimensional fine structures which have not been possible by the traditional...	01/04/2000
6007969	Ultra-fine microfabrication method using an energy beam An ultra-fine microfabrication method using an energy beam is based on the use of shielding provided by nanometer or micrometer sized micro-particles to produce a variety of three-dimensional fine structures which have not been possible by the traditional...	12/28/1999
5950106	Method of patterning a metal substrate using spin-on glass as a hard mask A method for patterning an underlying metal substrate includes forming a layer of spin-on glass over the metal substrate, forming a layer of photoresist over the spin-on glass, patterning the photoresist, patterning the spin-on glass using the photoresist...	09/07/1999
5894058	Ultra-fine microfabrication method using a fast atomic energy beam An ultra-fine microfabrication method using an energy beam is based on the use of shielding provided by nanometer or micrometer sized micro-particles to produce a variety of three-dimensional fine structures which have not been possible by the traditional...	04/13/1999
5891804	Process for conductors with selective deposition This is a method of forming a conductor 26 on an interlevel dielectric layer 12 which is over an electronic microcircuit substrate 10, and the structure produced thereby. The method utilizes: forming an intralevel dielectric layer 14 over the interlevel d...	04/06/1999
5871870	Mask for forming features on a semiconductor substrate and a method for forming the mask A mask and a method for forming a mask on a surface of an underlying layer of material used in semiconductor device manufacturing. The mask is a mixture of mask particles and spacer particles. The spacer particles space the mask particles apart from one a...	02/16/1999
5868952	Fabrication method with energy beam Three-dimensional ultra-fine micro-fabricated structures of the order of μm and less are produced for use in advanced optical communication systems and quantum effect devices. The basic components are an energy beam source, a mask member and a specimen s...	02/09/1999
5858847	Method for a lightly doped drain structure The present invention provides a method of manufacturing a lightly doped drain (LDD) structure using a polymer layer to define the LDD. The polymer layer is formed in an etch step which defines the gate electrode. The method begins by forming spaced field...	01/12/1999
5858861	Reducing nitride residue by changing the nitride film surface property A new method of changing the surface property of a nitride film from hydrophobic to hydrophillic and thereby reducing nitride residue after photolithography is described. A pad oxide layer is provided on the surface of a semiconductor substrate. A nitride...	01/12/1999
5830774	Method for forming a metal pattern on a substrate A method for forming a metal pattern on a substrate (11) includes forming a dielectric stack (14) on a major surface (12) of the substrate (11) and forming a mask (22) on the dielectric stack (14). The dielectric stack (14) includes an aluminum nitride la...	11/03/1998
5725788	Apparatus and method for patterning a surface An apparatus (95) and method for patterning a surface of an article (30), the apparatus (95) including a large-area stamp (50) for forming a self-assembled monolayer (36) (SAM) of a molecular species (38) on the surface (34) of a layer (32) of resist mate...	03/10/1998
5676853	Mask for forming features on a semiconductor substrate and a method for forming the mask A mask and a method for forming a mask on a surface of an underlying layer of material used in semiconductor device manufacturing. The mask is a mixture of mask particles and spacer particles. The spacer particles space the mask particles apart from one a...	10/14/1997
5641715	Semiconductor IC device fabricating method Either a chemical amplification positive electron beam resist film or a chemical amplification negative electron beam resist film is used selectively according to an IC fabricating process when forming a minute IC pattern by using, as a mask, a resist pat...	06/24/1997
5554488	Semiconductor device structure and method of formation thereof A method of forming a semiconductor structure, and a structure thereof are provided. The method is based on a novel lift-off masking process, and has particular application for forming gate structures for FETs with sputtered metals. After providing a weak...	09/10/1996
5541128	Self-aligned thin-film transistor constructed using lift-off technique In the fabrication of thin-film field-effect transistors, a dielectric island is first formed over a gate and between locations where source and drain contacts are to be deposited. A dielectric cap with an overhanging brim is formed on the island. A layer...	07/30/1996
5407529	Method for manufacturing semiconductor device In a pattern formation method which employs a resist system of tri-level structure the present method is characterized in that it uses a fluorine contained silicon dioxide film as the intermediate film. Since this fluorine contained silicon dioxide film c...	04/18/1995
5376229	Method of fabrication of adjacent coplanar semiconductor devices A method for processing coplanar semiconductor devices of different types as provided. The method includes the steps of: forming a first layer for formation of a first device region on a substrate, forming an epitaxial semiconductor lift-off layer above t...	12/27/1994
5240558	Method for forming a semiconductor device The surface area of a polysilicon electrode is increased by sputtering non-coalescing islands (20) of aluminum onto a silicon dioxide layer (18), which is overlying the polysilicon electrode. The sputtering process allows uniform island formation to be ac...	08/31/1993
4766093	Chemically formed self-aligned structure and wave guide The formation of a self-aligned semiconductor structure in a semiconductor substrate is described by providing a first and a second layer or a wave guide of different chemical composition above said semiconductor substrate, said second layer providing a s...	08/23/1988
4697333	Method of manufacturing a semiconductor device using amorphous silicon as a mask A method of manufacturing a semiconductor device has the steps of forming an insulating film on a semiconductor substrate, forming a polycrystalline silicon layer on the insulating film, converting either all of the polycrystalline silicon layer or a port...	10/06/1987
4654119	Method for making submicron mask openings using sidewall and lift-off techniques A method is disclosed for making submicron openings in a substrate. A mesa is formed on the substrate by reactive ion etching techniques. A film is deposited over the entire structure and the mesa is selectively etched away to yield a submicron-sized open...	03/31/1987
4637129	Selective area III-V growth and lift-off using tungsten patterning A method of device fabrication using selective area regrowth Group III-V compound semiconductors with tungsten patterning is described....	01/20/1987
4356056	Process for insulating the interconnections of integrated circuits The invention relates to integrated circuits in which each component is formed in an active layer, supported by an island, called mesa, of the substrate. With a view to forming a dielectric layer on the surface of the substrate and on the sides of the mes...	10/26/1982
4224361	High temperature lift-off technique A layer of resist is applied to a metal substrate, and a matrix is formed in the resist. A metal or dielectric mask having overhanging upper edges is formed by electroplating metal into the resist matrix which has preformed openings for defining the mask....	09/23/1980

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Class 257/E21.034 - For lift-off process (EPO)