Did You Know...
...that in the early 1940s GE engineer James Wright was charged with a task of utmost importance to the war effort: develop a cheap substitute for rubber that could be used to produce tires, gas masks and a whole host of military gear. Wright tackled the task diligently -- and wound up inventing Silly Putty.
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| Number | Title | Issue Date |
| 7432212 | Methods of processing a semiconductor substrate The invention includes methods of processing semiconductor substrates. In one implementation, a semiconductor substrate is provided which has an outer surface. Such surface has a peripheral region received about a peripheral edge of the semiconductor substrate. A la... | 10/07/2008 |
| 7416995 | Method for fabricating controlled stress silicon nitride films A method for fabricating a multiple layer silicon nitride film on a semiconductor substrate is provided herein. In one embodiment, a method for fabricating a multiple layer silicon nitride film on a semiconductor substrate includes providing a substrate over which t... | 08/26/2008 |
| 7393707 | Method for manufacturing an electro-optical device An object of the present invention is to provide an EL display device having high operation performance and reliability. A third passivation film 45 is disposed under the EL element 203 comprising a pixel electrode (anode) 46, an EL layer... | 07/01/2008 |
| 7329613 | Structure and method for forming semiconductor wiring levels using atomic layer deposition A method for forming a conductive wire structure for a semiconductor device includes defining a mandrel on a substrate, forming a conductive wire material on the mandrel by atomic layer deposition, and forming a liner material around the conductive wire material by ... | 02/12/2008 |
| 7288420 | Method for manufacturing an electro-optical device An object of the present invention is to provide an EL display device having high operation performance and reliability. A third passivation film 45 is disposed under the EL element 203 comprising a pixel electrode (anode) 46, an EL layer... | 10/30/2007 |
| 7241688 | Aperture masks for circuit fabrication Aperture masks and deposition techniques for using aperture masks are described. In addition, techniques for creating aperture masks and other techniques for using the aperture masks are described. The various techniques can be particularly useful in creating circui... | 07/10/2007 |
| 7192789 | Method for monitoring an ion implanter A method for monitoring an ion implanter is disclosed. In one embodiment, the method comprises providing a wafer, forming a barrier layer on the surface of the wafer wherein the barrier layer has a substantial blocking effect on ion implantation, performing an ion i... | 03/20/2007 |
| 7176053 | Laser ablation method for fabricating high performance organic devices A laser ablation method is utilized to define the channel length of an organic transistor. A substrate is coated with a deposition of a metal or conductive polymer deposition, applied in a thin layer in order to enhance the resolution that can be attained by laser a... | 02/13/2007 |
| 7172965 | Method for manufacturing semiconductor device After forming a stopper film on a semiconductor substrate having a copper wiring layer therein, an interlayer insulating film made of a low dielectric constant material is formed on the stopper film. Then, after forming a capping film on the interlayer insulating fi... | 02/06/2007 |
| 7138341 | Process for making a memory structure An exemplary method for making a memory structure comprises forming a first hard mask layer, forming at least one mask layer above the first hard mask layer, patterning the at least one mask layer, etching the at least one mask layer to form an opening having a firs... | 11/21/2006 |
| 7115524 | Methods of processing a semiconductor substrate The invention includes methods of processing semiconductor substrates. In one implementation, a semiconductor substrate is provided which has an outer surface. Such surface has a peripheral region received about a peripheral edge of the semiconductor substrate. A la... | 10/03/2006 |
| 6225217 | Method of manufacturing semiconductor device having multilayer wiring A first insulating film with a dielectric constant lower than that of a silicon oxide film is formed on a semiconductor substrate. Next, a metal film or a second insulating film, which has degrees of moisture absorption and deformation in an oxygen plasma... | 05/01/2001 |
| 6140225 | Method of manufacturing semiconductor device having multilayer wiring A first insulating film with a dielectric constant lower than that of a silicon oxide film is formed on a semiconductor substrate. Next, a second insulating film, which has degrees of moisture absorption and deformation in an oxygen plasma process and exp... | 10/31/2000 |
| 6025115 | Processing method for etching a substrate A processing method for etching a substrate is described. This method includes subjecting a surface of a substrate to be processed to selective irradiation with a light in a gas atmosphere to form a surface-modified layer. The substrate surface with the s... | 02/15/2000 |
| 5981001 | Processing method for selectively irradiating a surface in presence of a reactive gas to cause etching A processing method comprises: a first step of depositing on a substrate which is a specimen a film of any one of a semiconductor, a metal and an insulator; a second step of subjecting the surface of the film deposited in the first step, to irradiation with a ... | 11/09/1999 |
| 5962194 | Processing method and apparatus A processing method comprises: a first step of depositing on a substrate which is a specimen a film of any one of a semiconductor, a metal and an insulator; a second step of subjecting the surface of the film deposited in the first step, to irradiation with a ... | 10/05/1999 |
| 5863706 | Processing method for patterning a film A processing method is described which has a first step of depositing on a substrate a specimen film which may be any one of a semiconductor, a metal and a insulator. In a second step, the surface of the specimen film deposited in the first step, is irrad... | 01/26/1999 |
| 5847465 | Contacts for semiconductor devices A method for fabrication of metal to semiconductor contacts results in sloped sidewalls in contact regions. An oxide layer is deposited and etched back to form sidewall spacers. A glass layer is then deposited and heated to reflow. After reflow, an etch b... | 12/08/1998 |
| 5837560 | Method of masking substrates leaving exposed facets A method of masking a substrate to leave an exposed facet for processing during fabrication of a semiconductor devices including providing a substrate formed of a semiconductor material and having a structure projecting therefrom, the structure including ... | 11/17/1998 |
| 5824455 | Processing method and apparatus A processing method comprises: a first step of depositing on a substrate which is a specimen a film of any one of a semiconductor, a metal and an insulator; a second step of subjecting the surface of the film deposited in the first step, to irradiation with a ... | 10/20/1998 |
| 5714306 | Processing method and apparatus A processing method comprises: a first step of depositing on a substrate which is a specimen a film of any one of a semiconductor, a metal and an insulator; a second step of subjecting the surface of the film deposited in the first step, to irradiation with a ... | 02/03/1998 |
| 5528058 | IGBT device with platinum lifetime control and reduced gaw For IGBT, MCT or like devices, the substrate is formed with P+, N+ and N- layers and PN diffusions to define body and source regions in the N-layer and a MOS-gated channel at the upper surface. The N-layer is sized and doped (~1014 /cm3 | 06/18/1996 |
| 5409566 | Slope etching process A slope etching process including dipping a pattern forming layer into a predetermined dipping solution containing an etching solution or wet etching and deionized water, so as to utilize a wet etching method only for isotropic etching. There is also prov... | 04/25/1995 |
| 5334550 | Method of producing a self-aligned window at recessed intersection of insulating regions An integrated circuit structure and process relating to a self-aligned window at the recessed junction of two insulating regions formed on the surface of a semiconductor body. The window may include a trench forming an isolation region between doped semic... | 08/02/1994 |
| 5283202 | IGBT device with platinum lifetime control having gradient or profile tailored platinum diffusion regions For IGBT, MCT or like devices, the substrate is formed with P+, N+ and N- layers and PN diffusions to define body and source regions in the N-layer and a MOS-gated channel at the upper surface. The N-layer is sized and doped (~1014 /cm3 | 02/01/1994 |
| 5283201 | High density power device fabrication process A recessed gate power MOSFET is formed on a substrate (20) including a P-body layer (26), N-drain layer (24) and optional P+ layer (22) for IGBT. A trenching protective layer (30) formed on the substrate upper surface (28) is patterned to define exposed a... | 02/01/1994 |
| 5262336 | IGBT process to produce platinum lifetime control For IGBT, MCT or like devices, the substrate is formed with P+, N+ and N- layers and PN diffusions to define body and source regions in the N-layer and a MOS-gated channel at the upper surface. The N-layer is sized and doped (~1014 /cm3 | 11/16/1993 |
| 5256583 | Mask surrogate semiconductor process with polysilicon gate protection A dopant-opaque layer of polysilicon is deposited on gate oxide on the upper substrate surface to serve as a pattern definer during fabrication of the device. It provides control over successive P and N doping steps used to create the necessary operative ... | 10/26/1993 |
| 5246879 | Method of forming nanometer-scale trenches and holes Nanometer thick metallic layers are fabricated on trenches or holes (espelly vias) within a substrate by depositing, by thermal decomposition of a volatile metal-containing precursor gas in the presence of a carrier gas at low pressure, a metallic layer ... | 09/21/1993 |
| 5212103 | Method of making a heterojunction bipolar transistor A semiconductor device includes an n+ type InGaAs layer at a surface of the device, a refractory metal emitter electrode making ohmic contact to the n+ layer without alloying and an externally accessible base region produced in the n... | 05/18/1993 |
| 5204276 | Method of manufacturing semiconductor device In the method of manufacturing a semiconductor device, a buffer oxide film, an oxidation-resistant film and a first poly-Si film containing a p-type impurity are successively formed to form a laminate structure on the n-type collector region, followed by ... | 04/20/1993 |
| 5182234 | Profile tailored trench etch using a SF6 -O2 etching composition wherein both isotropic and anisotropic etching is achieved by varying the amount of oxygen A dopant-opaque layer of polysilicon is deposited on gate oxide on the upper substrate surface to serve as a pattern definer during fabrication of the device. It provides control over successive P and N doping steps used to create the necessary operative ... | 01/26/1993 |
| 5127989 | Method of forming a thin film pattern with a trapezoidal cross section The present invention provides a method of forming a thin film pattern with a trapezoidal cross section. In this method, a resist pattern with an inverted-trapezoidal cross section is formed on a thin film. Using the resist pattern with the inverted-trape... | 07/07/1992 |
| 5119150 | Compound semiconductor structure including layer limiting silicon diffusion A semiconductor structure includes a compound semiconductor substrate, a compound semiconductor diffusion limiting layer containing aluminum, disposed on the substrate, and having a larger aluminum content than the substrate, a compound semiconductor laye... | 06/02/1992 |
| 5110760 | Method of nanometer lithography Nanometer thick vertical metallic structures are fabricated on a substrate by depositing a metallic layer on a substrate surface on which one or more buttresses are formed, etching the metallic layer to expose the horizontal surfaces of the substrate and ... | 05/05/1992 |
| 5100813 | Method of manufacturing bipolar transistor A method of manufacturing a bipolar transistor. A first mask material film pattern is formed on an internal base region prospective portion on a collector region of a first conductive type, and then a first conductive film is deposited. A recess around th... | 03/31/1992 |
| 5089434 | Mask surrogate semiconductor process employing dopant-opaque region A dopant-opaque layer of polysilicon is deposited on gate oxide on the upper substrate surface to serve as a pattern definer during fabrication of the device. It provides control over successive P and N doping steps used to create the necessary operative ... | 02/18/1992 |
| 5079177 | Process for fabricating high performance BiCMOS circuits A method of making complementary vertical bipolar transistors and complementary field effect transistors on the same substrate is described. The process includes forming buried layers in a semiconductor substrate which are spaced apart in a self-aligned m... | 01/07/1992 |
| 5073812 | Heterojunction bipolar transistor A semiconductor device includes an n+ type InGaAs layer at a surface of the device, a refractory metal emitter electrode making ohmic contact to the n+ layer without alloying, and an externally accessible base region produced in th... | 12/17/1991 |
| 5070029 | Semiconductor process using selective deposition A process for fabricating semiconductor devices is disclosed which utilizes a selective deposition process to reduce the total number of process steps and especially the total number of photolithography steps required. In accordance with one embodiment of... | 12/03/1991 |
