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| Number | Title | Issue Date |
| 7425492 | Use of an internal on-chip inductor for electrostatic discharge protection of circuits which use bond wire inductance as their load A method for forming and packaging an integrated circuit having a plurality of circuit components on a semi conductive substrate die. The plurality of circuit components include at least one active component that operates on an information signal, a tuning node coup... | 09/16/2008 |
| 7422941 | High performance system-on-chip using post passivation process The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In ad... | 09/09/2008 |
| 7399696 | Method for high performance inductor fabrication using a triple damascene process with copper BEOL A method of forming a high performance inductor comprises providing a substrate; forming a plurality of wiring levels over the substrate, wherein each of the wiring levels comprise a dielectric layer; forming a first trench having a first depth in a first dielectric... | 07/15/2008 |
| 7400025 | Integrated circuit inductor with integrated vias Integrated circuit inductors (5) are formed by interconnecting various metal layers (10) in an integrated circuit with continuous vias (200). Using continuous vias (200) improves the Q factor over existing methods for high frequency appli... | 07/15/2008 |
| 7390736 | EMI and noise shielding for multi-metal layer high frequency integrated circuit processes A circuit element that may generate or be affected by noise or electromagnetic interference may be substantially surrounded by one or more encircling plugs. The encircling plug may be closed by an interconnection layer. The plug may be grounded to reduce the electro... | 06/24/2008 |
| 7375000 | Discrete on-chip SOI resistors A semiconductor resistor, method of making the resistor and method of making an IC including resistors. Buried wells are formed in the silicon substrate of a silicon on insulator (SOI) wafer. At least one trench is formed in the buried wells. Resistors are formed al... | 05/20/2008 |
| 7354799 | Methods for anchoring a seal ring to a substrate using vias and assemblies including an anchored seal ring Disclosed are embodiments of a method for forming a seal ring on a substrate that is anchored to the substrate by a number of vias. Also disclosed are embodiments of an assembly including such an anchored seal ring. In some embodiments, a seal ring may extend around... | 04/08/2008 |
| 7285840 | Apparatus for confining inductively coupled surface currents A deep n-well is formed beneath the area of an inductor coil. The use of a deep n-well lessens the parasitic capacitance by placing a diode in series with the interlayer dielectric cap. The deep n-well also reduces substrate noise. Once the n-well is implanted and a... | 10/23/2007 |
| 7268409 | Spiral inductor with electrically controllable resistivity of silicon substrate layer A microelectronic device including, in one embodiment, a plurality of active devices located at least partially in a substrate, at least one dielectric layer located over the plurality of active devices, and an inductor located over the dielectric layer. At least on... | 09/11/2007 |
| 7264986 | Microelectronic assembly and method for forming the same According to one aspect of the present invention, a method is provided for forming a microelectronic assembly. The method comprises forming first and second trenches on a semiconductor substrate, filling the first and second trenches with an etch stop material, form... | 09/04/2007 |
| 7250669 | Process to reduce substrate effects by forming channels under inductor devices and around analog blocks A first method of reducing semiconductor device substrate effects comprising the following steps. O+or O2+are selectively implanted into a silicon substrate to form a silicon-damaged silicon oxide region. One or more devices are form... | 07/31/2007 |
| 7247542 | Fabrication method of spiral inductor on porous glass substrate The present invention discloses a fabrication method and structure of spiral RF inductor on porous glass substrate. Thick porous silicon layer is natively formed on a silicon wafer by anodic etching the silicon material to a high degree of porosity. The porous silic... | 07/24/2007 |
| 7229908 | System and method for manufacturing an out of plane integrated circuit inductor A system and method is described for manufacturing an out of plane integrated circuit inductor. A plurality of parallel metal bars are formed on a substrate and covered with a first passivation layer. A ferromagnetic core is then deposited over the first passivation... | 06/12/2007 |
| 7196397 | Termination design with multiple spiral trench rings A semiconductor device having a termination structure, which includes at least one spiral resistor disposed within a spiral trench and connected between two power poles of the device. ... | 03/27/2007 |
| 7170181 | Optimum padset for wire bonding RF technologies with high-Q inductors An RF structure that includes an optimum padset for wire bonding and a high performance inductor that contains relatively thick metal inductor wires, both of which are located atop the final interconnect level of an interconnect structure. Specifically, the RF struc... | 01/30/2007 |
| 7161227 | Structure and method for fabricating semiconductor structures and devices for detecting an object High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of mono... | 01/09/2007 |
| 7148535 | Zero capacitance bondpad utilizing active negative capacitance The present invention is an apparatus and system for reducing bondpad capacitance of an integrated circuit. Circuitry of the present invention may produce a negative capacitance approximately equal in magnitude to the capacitance associated with the bondpad and ther... | 12/12/2006 |
| 7118925 | Fabrication of a ferromagnetic inductor core and capacitor electrode in a single photo mask step A method of manufacturing an integrated circuit on a semiconductor wafer. The method comprising forming a bottom plate of a capacitor 50a and a bottom portion of an induction coil 50a, forming an etch stop layer 250′, forming a f... | 10/10/2006 |
| 6806805 | Low loss high Q inductor A high Q inductive clement with low losses, high inductance and high efficiency is disclosed. The high Q inductive element with one or more inductive loops is formed over a silicon micro structure with thin support elements formed by deep plasma etching in bulk sili... | 10/19/2004 |
| 6686825 | Chip inductor and manufacturing method therefor A chip inductor has electrode layers, insulating layers disposed on the electrode layers, and an uppermost insulating layer all disposed on a ceramic board. An inorganic pigment such as a Co oxide or an Al oxide is added to the insulating layer at a conce... | 02/03/2004 |
| 6680518 | Monolithic inductance-enhancing integrated circuits, complementary metal oxide semiconductor (CMOS) inductance-enhancing integrated circuits, inductor assemblies, and inductance-multiplying methods Monolithic inductance-enhancing integrated circuits, complementary metal oxide semiconductor (CMOS) inductance-enhancing integrated circuits, inductor assemblies, and inductance-multiplying methods are described. In one embodiment, a monolithic inductance... | 01/20/2004 |
| 6667217 | Method of fabricating a damascene copper inductor structure using a sub-0.18 um CMOS process A process for integrating the fabrication of a thick, copper inductor structure, with the fabrication of narrow channel length CMOS devices, has been developed. The integrated process features the use of only one additional photolithographic masking step,... | 12/23/2003 |
| 6667536 | Thin film multi-layer high Q transformer formed in a semiconductor substrate A thin-film multi-layer high Q transformer. To form an outer transformer winding a plurality of parallel first level metal runners are formed in a first insulating layer overlying the semiconductor substrate. A plurality of vertical conductive vias are fo... | 12/23/2003 |
| 6661079 | Semiconductor-based spiral capacitor Increased capacitance per unit of area with reduced series resistance and inductance is provided by a semiconductor-based capacitor with a spiral shape. The capacitor utilizes a plurality of patterned metal layers that each have a first trace with a spira... | 12/09/2003 |
| 6661078 | Inductance element and semiconductor device The inductance element according to the present invention includes: an inductance section, provided above a semiconductor substrate via insulating films, which is composed of a conductive film pattern setted to have a predetermined inductance value; and a... | 12/09/2003 |
| 6657310 | Top layers of metal for high performance IC's A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or pol... | 12/02/2003 |
| 6656813 | Low loss high Q inductor A high Q inductive element with low losses, high inductance and high efficiency is disclosed. The high Q inductive element with one or more inductive loops is formed over a silicon micro structure with thin support elements formed by deep plasma etching i... | 12/02/2003 |
| 6654210 | Solid-state inductor and method for same A solid-state inductor and a method for forming a solid-state inductor are provided. The method comprises: forming a bottom electrode; forming a colossal magnetoresistance (CMR) thin film overlying the bottom electrode; forming a top electrode overlying t... | 11/25/2003 |
| 6653196 | Open pattern inductor The invention includes a stacked open pattern inductor fabricated above a semiconductor substrate. The stacked open pattern inductor includes a plurality of parallel open conducting patterns embedded in a magnetic oxide or in an insulator and a magnetic m... | 11/25/2003 |
| 6650220 | Parallel spiral stacked inductor on semiconductor material A parallel spiral stacked inductor and manufacturing method therefore is provided. A substrate has a plurality of turns in a plurality of levels, the plurality of turns having a center proximate and a center distal ends. A first plurality of vias connecti... | 11/18/2003 |
| 6642540 | Semiconductor integrated circuit device A semiconductor device is arranged by having a shield/planarization portion including a silicided active region formed on the main surface of a semiconductor substrate and a non-active region provided by device-isolation on the surface, and a metal layer ... | 11/04/2003 |
| 6639298 | Multi-layer inductor formed in a semiconductor substrate A thin-film multi-layer high Q inductor spanning at least three metal layers is formed by forming a plurality of parallel first metal runners on the semiconductor substrate. A plurality of first and second vertical conductive vias are formed in electrical... | 10/28/2003 |
| 6635949 | Symmetric inducting device for an integrated circuit having a ground shield The present invention relates to integrated circuits having symmetric inducting devices with a ground shield. In one embodiment, a symmetric inducting device for an integrated circuit comprises a substrate, a main metal layer and a shield. The substrate h... | 10/21/2003 |
| 6635550 | Semiconductor on insulator device architecture and method of construction An SOI architecture is provided that comprises an inner substrate 10 which has a buried conductor layer 12 formed on an outer surface thereof. A bonding layer 14 is used to provide a cohesive bond with a buried insulator layer 18. The semiconductor device... | 10/21/2003 |
| 6635948 | Semiconductor device with electrically coupled spiral inductors Multiple coupled inductors are formed in a well in a semiconductor device. The inductors, which preferably are spiral inductors, are strongly coupled with high quality factors. The coupled inductors may be used as efficient signal splitting and combining ... | 10/21/2003 |
| 6627507 | Integrated circuit and method of using porous silicon to achieve component isolation in radio frequency applications The invention relates to an improved substrate (100) using a layer (112) or region (130) of porous silicon that is created in the bulk silicon substrate material (110) to increase the resistivity of the substrate (100) thus making it suitable for passive ... | 09/30/2003 |
| 6617665 | High-frequency integrated inductive winding An inductance formed in an integrated circuit chip, formed of a plurality of parallel conductive lines, of optimized width, each conductive line being formed in the thickness of at least one insulating layer, these lines being interconnected by at least o... | 09/09/2003 |
| 6614093 | Integrated inductor in semiconductor manufacturing An integrated inductor is formed on an integrated circuit or other substrate. The inductor is formed of a stack of almost totally enclosed rings of conductive material in which each ring has a single gap. Vias connect adjacent rings on opposite sides of t... | 09/02/2003 |
| 6608364 | Semiconductor device comprising windings constituting inductors Semiconductor device comprising a metal circuit with two parts wound into spirals which are formed such that the branches of one of the parts and the corresponding branches of the other part lie on either side of a median longitudinal region and are symme... | 08/19/2003 |
| 6605857 | Reducing magnetic coupling using triple well An integrated inductive element may be formed over a substrate. A triple well may be defined in a star-shape, in one embodiment, in the substrate beneath the integrated inductive element in order to reduce eddy current losses arising from magnetic couplin... | 08/12/2003 |
