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| Number | Title | Issue Date |
| 7405418 | Memory device electrode with a surface structure The invention relates to a memory device electrode, in particular for a resistively switching memory device, wherein the surface of the electrode is provided with a structure, in particular comprises one or a plurality of shoulders or projections, respectively. Furt... | 07/29/2008 |
| 7335526 | Sensing system A ChemFET Sensing system is Described. ... | 02/26/2008 |
| 7262108 | Methods for forming resistors for integrated circuit devices Methods of forming an integrated circuit device may include forming an insulating layer on an integrated circuit substrate, forming a first conductive layer on the insulating layer, and forming a second conductive layer on the first conductive layer so that the firs... | 08/28/2007 |
| 7241700 | Methods for post offset spacer clean for improved selective epitaxy silicon growth A gate structure is formed overlying a substrate. A source/drain region of the substrate is exposed to a soluction comprising ammonium hydroxide, hydrogen peroxide, and deionized water to etch an upper-most semiconductor porton of the source/drain region. ... | 07/10/2007 |
| 7187085 | Semiconductor device including dual damascene interconnections A method (and structure) of forming an interconnect on a semiconductor substrate, includes forming a relatively narrow first structure in a dielectric formed on a semiconductor substrate, forming a relatively wider second structure in the dielectric formed on the se... | 03/06/2007 |
| 7115531 | Organosilicate resins as hardmasks for organic polymer dielectrics in fabrication of microelectronic devices This invention is a method comprising providing a substrate, forming a first layer on the substrate, wherein the first layer has a dielectric constant of less than 3.0 and comprises an organic polymer, applying an organosilicate resin over the first layer, removing ... | 10/03/2006 |
| 6693002 | Semiconductor device and its manufacture A semiconductor device having: a substrate having a first area and a second area surrounding the first area; an insulating film formed in the second area; electrodes formed above the surface of the substrate in the first area; dielectric films formed abov... | 02/17/2004 |
| 6646299 | Integrated circuit configuration having at least two capacitors and method for manufacturing an integrated circuit configuration A first capacitor electrode and at least part of a second capacitor electrode of a capacitor are produced in depressions of an auxiliary layer by electroplating. The auxiliary layer is then removed and at least partially replaced by a capacitor dielectric... | 11/11/2003 |
| 6608344 | Structure and manufacturing method of semiconductor device having uneven surface at memory cell capacitor part A structure and a manufacturing method of a semiconductor device composed of 1T1Cs, in which a surface area of a memory cell capacitor part is expanded by forming an uneven surface at the memory cell capacitor part, is provided. Further, an additional pho... | 08/19/2003 |
| 6586794 | Semiconductor device and its manufacture A semiconductor device having: a substrate having a first area and a second area surrounding the first area; an insulating film formed in the second area; electrodes formed above the surface of the substrate in the first area; dielectric films formed abov... | 07/01/2003 |
| 6580112 | Method for fabricating an open can-type stacked capacitor on an uneven surface An open can-type stacked capacitor is fabricated by forming a conductive layer (30, 130) outwardly of a substantially uneven surface (12, 112). A step (50, 150) is formed in an outer surface (32, 132) of the conductive layer (30, 130). A base (72, 172, 20... | 06/17/2003 |
| 6573554 | Localized masking for semiconductor structure development Container structures for use in integrated circuits and methods of their manufacture without the use of mechanical planarization such as chemical-mechanical planarization (CMP), thus eliminating CMP-induced defects and variations. The methods utilize loca... | 06/03/2003 |
| 6566702 | Spacer patterned, high dielectric constant capacitor A high dielectric constant memory cell capacitor and method for producing the same, wherein the memory cell capacitor utilizes relatively large surface area conductive structures of thin spacer width pillars or having edges without sharp corners that lead... | 05/20/2003 |
| 6558999 | Method for forming a storage electrode on a semiconductor device The present invention provides a method for forming a storage electrode on a semiconductor substrate, and in particular to a storage electrode formation method which can prevent formation of a sharp upper edged cylindrical storage electrode, thereby impro... | 05/06/2003 |
| 6548346 | Process for forming DRAM cell A transfer FET of a DRAM cell is formed having protective dielectric layers on the top and sides of the gate electrode. A first dielectric layer, preferably silicon dioxide, is provided over the transfer FET and a self-aligned etching process is used to e... | 04/15/2003 |
| 6514812 | Structure and manufacturing method of semiconductor device having uneven surface at memory cell capacitor part A structure and a manufacturing method of a semiconductor device composed of 1T1Cs, in which a surface area of a memory cell capacitor part is expanded by forming an uneven surface at the memory cell capacitor part, is provided. Further, an additional pho... | 02/04/2003 |
| 6506660 | Semiconductor with nanoscale features Described is a method of increasing the capacitance of semiconductor capacitors by providing a first solid-state electrode pattern on a semiconductor medium, etching topographic features on said first electrode pattern in a manner effective in increasing ... | 01/14/2003 |
| 6458654 | Large surface area capacitor and methods for fabricating same A high dielectric constant memory cell capacitor and method for producing the same, wherein the memory cell capacitor utilizes relatively large surface area conductive structures of thin spacer width pillars or having edges without sharp corners that lead... | 10/01/2002 |
| 6451650 | Low thermal budget method for forming MIM capacitor The next generation of DRAM capacitors will require base electrodes having large effective surface areas and, additionally, will need to be manufactured with the expenditure of minimal energy (low thermal budgets). This is achieved in the present inventio... | 09/17/2002 |
| 6448605 | Method of fabricating gate A method of fabricating a gate is described. A first dielectric layer having a first opening is formed on a substrate. A gate dielectric layer is formed in the opening. A lower portion of a floating gate is formed on the gate dielectric layer. A source/dr... | 09/10/2002 |
| 6404005 | Methods of forming capacitors and related integrated circuitry Capacitor constructions and methods of forming the same are described. In one implementation, a capacitor container is formed over a substrate and includes an internal surface and an external surface. At least some of the external surface is provided to b... | 06/11/2002 |
| 6391708 | Method of manufacturing DRAM capacitor A method of manufacturing a DRAM capacitor comprises the steps of providing a semiconductor substrate having a source/drain region thereon, and then forming an insulating layer over the substrate. Next, a storage node opening that exposes the source/drain... | 05/21/2002 |
| 6387750 | Method of forming MIM capacitor A method of forming a metal-insulator-metal (MIM) capacitor is disclosed. The method provides a three dimensional MIM capacitor having upgraded capacitance. A plurality of trenches are formed within the MIM capacitor to increase the charge storage area of... | 05/14/2002 |
| 6387752 | Semiconductor memory device and method of fabricating the same There is provided a method of fabricating a semiconductor memory device including a memory cell having transistor and a capacitor, and a cylindrical accumulation electrode, the method including the steps of (a) forming a first insulating film on a lower i... | 05/14/2002 |
| 6358793 | Method for localized masking for semiconductor structure development Container structures for use in integrated circuits and methods of their manufacture without the use of mechanical planarization such as chemical-mechanical planarization (CMP), thus eliminating CMP-induced defects and variations. The methods utilize loca... | 03/19/2002 |
| 6358813 | Method for increasing the capacitance of a semiconductor capacitors Described is a method of increasing the capacitance of semiconductor capacitors by providing a first solid-state electrode pattern on a semiconductor medium, etching topographic features on said first electrode pattern in a manner effective in increasing ... | 03/19/2002 |
| 6352932 | Methods of forming integrated circuitry and integrated circuitry structures In one aspect, a plurality of layers are formed over a substrate and a series of first trenches are etched into a first of the layers in a first direction. A series of second trenches are etched into the first layer in a second direction which is differen... | 03/05/2002 |
| 6346724 | Semiconductor memory device having a capacitor over bit-line structure and method for manufacturing the same A semiconductor memory device having an improved step profile between a cell array region and peripheral circuit region, and a method for manufacturing the same, are provided. The semiconductor memory device has a cell array region and a peripheral circui... | 02/12/2002 |
| 6337173 | Method for fabricating a semiconductor capacitor A method for fabricating a capacitor electrode on a semiconductor substrate includes the steps of: forming a conducting layer over the semiconductor substrate; forming a photoresist layer over the conducting layer; pattering the photoresist layer through ... | 01/08/2002 |
| 6335257 | Method of making pillar-type structure on semiconductor substrate The present invention provides a method in making a pillar-type structure (e.g. a storage node of stack capacitor) on a semiconductor substrate. By depositing a conductive polysilicon electrode layer, a nitride layer and a silicon layer on the substrate, ... | 01/01/2002 |
| 6326276 | Method for forming a capacitor in dram A method for forming a capacitor in DRAM is disclosed. The method includes: providing a conductor defined on a first dielectric layer; forming a second dielectric layer on the conductor; then forming a polysilicon layer on the second dielectric layer, the... | 12/04/2001 |
| 6319771 | Fabrication process for a lower electrode of a memory capacitor A fabrication process for a lower electrode of a memory capacitor, which process is performed on a substrate already having a first insulating layer formed thereon. First, a self-aligned contact opening is formed in a first insulating layer. The self-alig... | 11/20/2001 |
| 6312986 | Concentric container fin capacitor and method A container capacitor and method having an internal concentric fin. In one embodiment, the finned capacitor is a stacked container capacitor in a dynamic random access memory circuit. The finned container capacitor provides a high storage capacitance with... | 11/06/2001 |
| 6300196 | Method of fabricating gate A method of fabricating a gate is described. A first dielectric layer having a first opening is formed on a substrate. A gate dielectric layer is formed in the opening. A lower portion of a floating gate is formed on the gate dielectric layer. A source/dr... | 10/09/2001 |
| 6291293 | Method for fabricating an open can-type stacked capacitor on an uneven surface An open can-type stacked capacitor is fabricated by forming a conductive layer (30, 130) outwardly of a substantially uneven surface (12, 112). A step (50, 150) is formed in an outer surface (32, 132) of the conductive layer (30, 130). A base (72, 172, 20... | 09/18/2001 |
| 6288423 | Composite gate structure memory cell having increased capacitance A semiconductor device of the present invention is a semiconductor memory having a charge storage film. Recesses or holes which effectively increase the capacitance of a floating gate or a memory cell capacitor are formed in the charge storage film. These... | 09/11/2001 |
| 6284595 | Method for fabricating stacked capacitor having excellent anti-oxidation property A stacked capacitor includes a top electrode, a capacitor insulator film made of BST, and a bottom electrode having a hollow cylindrical shape and connected through a contact plug to a diffused region of a silicon substrate. The bottom electrode includes ... | 09/04/2001 |
| 6265263 | Method for forming a DRAM capacitor with porous storage node and rugged sidewalls The method for forming a DRAM capacitor can include the following steps. First, a first dielectric layer is formed on a semiconductor substrate, followed by the formation of a second dielectric layer on the first dielectric layer, and the formation of a t... | 07/24/2001 |
| 6235576 | Method for manufacturing a cylindrical capacitor A method for manufacturing a cylindrical capacitor on a substrate includes the steps of providing a semiconductor substrate having a first conductive layer thereon, and then forming an insulation layer over the first conductive layer. The insulation layer... | 05/22/2001 |
| 6236080 | Method of manufacturing a capacitor for high density DRAMs A method for manufacturing an integrated circuit capacitor is provided in the present invention. First, a semiconductor substrate is etched to form a contact hole. A conducting plug is then formed into the contact hole. Next, a dielectric layer is formed ... | 05/22/2001 |
