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| Number | Title | Issue Date |
| 7427545 | Trench memory cells with buried isolation collars, and methods of fabricating same The present invention relates to semiconductor devices, preferably dynamic random access memory (DRAM) cells, each of which contains at least one trench capacitor with a buried isolation collar. The trench capacitor is located in a trench in a semiconductor substrat... | 09/23/2008 |
| 7408216 | Device, system, and method for a trench capacitor having micro-roughened semiconductor surfaces Some embodiments of the invention include a memory cell having a vertical transistor and a trench capacitor. The trench capacitor includes a capacitor plate with a roughened surface for increased surface area. Other embodiments are described and claims. ... | 08/05/2008 |
| 7405418 | Memory device electrode with a surface structure The invention relates to a memory device electrode, in particular for a resistively switching memory device, wherein the surface of the electrode is provided with a structure, in particular comprises one or a plurality of shoulders or projections, respectively. Furt... | 07/29/2008 |
| 7354823 | Methods of forming integrated circuit devices having carbon nanotube electrodes therein An integrated circuit capacitor includes first and second electrodes and at least one dielectric layer extending between the first and second electrodes. The first electrode includes at least one carbon nanotube. The capacitor further includes an electrically conduc... | 04/08/2008 |
| 7341906 | Method of manufacturing sidewall spacers on a memory device, and device comprising same The present invention is generally directed to a method of manufacturing sidewall spacers on a memory device, and a memory device comprising such sidewall spacers. In one illustrative embodiment, the method includes forming sidewall spacers on a memory device compri... | 03/11/2008 |
| 7322098 | Method of simultaneous two-disk processing of single-sided magnetic recording disks Various methods and apparatus for simultaneously processing two single-sided hard memory disks is provided. Disks are positioned in pairs, with one surface of one disk positioned adjacent one surface of the second disk, with the disk surfaces touching or with a slig... | 01/29/2008 |
| 7276412 | MIM capacitor of semiconductor device and manufacturing method thereof In a capacitor of a semiconductor device, a bottom electrode is formed on a substrate and has an uneven top surface. An interlayer insulation layer is formed on the substrate and has a via hole exposing the top surface of the bottom electrode. A dielectric layer is ... | 10/02/2007 |
| 7253102 | Methods for forming and integrated circuit structures containing enhanced-surface-area conductive layers An enhanced-surface-area conductive layer compatible with high-dielectric constant materials is created by forming a film or layer having at least two phases, at least one of which is electrically conductive. The film may be formed in any convenient manner, such as ... | 08/07/2007 |
| 7247177 | Production method for electric double-layer capacitor A method of manufacturing electric double layer capacitors is disclosed. The method assumes a model in which solute is dissolved in solvent before preparing electrolyte, and estimates a withstanding voltage through a simulation. The electrolyte, of which withstandin... | 07/24/2007 |
| 7112505 | Method of selectively etching HSG layer in deep trench capacitor fabrication The invention provides a method of selectively etching a Hemispherical Silicon Grain (HSG) layer during deep trench capacitor fabrication. A substrate having a pad structure and a deep trench is provided. A buried oxide layer is formed on the upper sidewall of the d... | 09/26/2006 |
| 6690570 | Highly efficient capacitor structures with enhanced matching properties The present specification discloses highly efficient capacitor structures. One embodiment of the present invention is referred to herein as a vertical parallel plate (VPP) structure. In accordance with this embodiment, a capacitor structure having a plura... | 02/10/2004 |
| 6682984 | Method of making a concave capacitor The present invention is directed to fabrication of a capacitor formed with a substantially concave shape and having optional folded or convoluted surfaces. The concave shape optimizes surface area within a small volume and thereby enables the capacitor t... | 01/27/2004 |
| 6670663 | DRAM cell capacitor and manufacturing method thereof A method for manufacturing a cell capacitor includes a step of forming an upper electrode and a trench for the lower electrode simultaneously in a single mask step. Further steps for manufacturing a cell capacitor includes forming a storage node contact b... | 12/30/2003 |
| 6642565 | Miniaturized capacitor with solid-state dielectric, in particular for integrated semiconductor memories, E.G. DRAMS, and method for fabricating such a capacitor A dynamic random access memory capacitor and to a method for producing the same are described. A first (bottom) electrode of the capacitor has a grained surface made of tungsten silicide placed on a tungsten silicide layer which is disposed near a surface... | 11/04/2003 |
| 6617208 | High capacitance damascene capacitors The invention describes a high capacitance damascene capacitor. A etch-stop/capacitor dielectric layer 60 is sandwiched between two conductive plates 40 and 75 to form an integrated circuit capacitor. One metal plate 40 is copper formed using a damascene ... | 09/09/2003 |
| 6600209 | Mesh capacitor structure in an integrated circuit A mesh capacitor structure in an integrated circuit can be made up by arranging at least a unit capacitor module in a coupling way, thereby enhancing its total capacitance by coupling capacitance. The unit capacitor module includes a plurality of first co... | 07/29/2003 |
| 6586329 | Semiconductor device and a method of manufacturing thereof A contact hole having an opening diameter smaller than the minimum dimension that can be formed by photolithographic technique is formed. Using an interlayer insulating film 8 formed on a semiconductor substrate as an etching mask, etching is carried out ... | 07/01/2003 |
| 6583022 | Methods of forming roughened layers of platinum and methods of forming capacitors In one aspect, the invention includes a method of forming a roughened layer of platinum, comprising: a) providing a substrate within a reaction chamber; b) flowing an oxidizing gas into the reaction chamber; c) flowing a platinum precursor into the reacti... | 06/24/2003 |
| 6576947 | Cylindrical capacitor and method for fabricating same A method for fabricating a cylindrical capacitor that exceeds photolithographic resolution. The capacitor is formed by partially etching the storage node opening, thereby reducing the distance between adjacent openings defined by the photolithographic pro... | 06/10/2003 |
| 6573552 | Method to form hemispherical grained polysilicon A capacitor with Enhanced capacitance per cell area is provided. A container supported by a substrate is formed, followed by a first layer of undoped substantially amorphous silicon. Next, a layer of heavily doped amorphous silicon is formed on the first ... | 06/03/2003 |
| 6570210 | Multilayer pillar array capacitor structure for deep sub-micron CMOS A capacitor structure, especially for use in deep sub-micron CMOS, having an array of electrically conductive pillars which form the plates of the capacitor. Each of the pillars is formed by electrically conductive lines segments from at least two differe... | 05/27/2003 |
| 6555432 | Integrated capacitor bottom electrode for use with conformal dielectric Disclosed is a capacitor construction for a more uniformly thick capacitor dielectric layer, and a method for fabricating the same. The method has special utility where the bottom electrode comprises composite layers over which the capacitor dielectric de... | 04/29/2003 |
| 6542351 | Capacitor structure In a capacitive structure of an integrated circuit a comb-like configuration or other thin element configuration provides for capacitive coupling between electrode elements in one plane. By forming electrodes in a plurality of planes and selectively shift... | 04/01/2003 |
| 6541809 | Method of making straight wall containers and the resultant containers A method for providing semiconductor openings having a substantially straight wall or other desired etch profile. An etchable material layer is formed having target dopant levels or other etch rate varying characteristics to compensate for the characteris... | 04/01/2003 |
| 6509245 | Electronic device with interleaved portions for use in integrated circuits A capacitor for use in integrated circuits comprises a layer of conductive material. The layer of conductive material including at least a first portion and a second portion, wherein the first portion and the second portion are arranged in a predetermined... | 01/21/2003 |
| 6507065 | Doped silicon structure with impression image on opposing roughened surfaces A silicon structure is formed that includes a free-standing wall having opposing roughen ed inner and outer surfaces using ion implantation and an unplanted silicon etching process which is selective to implanted silicon. In general, the method provides a... | 01/14/2003 |
| 6482736 | Methods for forming and integrated circuit structures containing enhanced-surface-area conductive layers An enhanced-surface-area conductive layer compatible with high-dielectric constant materials is created by forming a film or layer having at least two phases, at least one of which is electrically conductive. The film may be formed in any convenient manne... | 11/19/2002 |
| 6479343 | DRAM cell capacitor and manufacturing method thereof A method for manufacturing a cell capacitor includes a step of forming an upper electrode and a trench for the lower electrode simultaneously in a single mask step. Further steps for manufacturing a cell capacitor includes forming a storage node contact b... | 11/12/2002 |
| 6472320 | Method of producing rough polysilicon by the use of pulsed plasma chemical vapor deposition and products produced by the same A method for depositing a rough polysilicon film on a substrate is disclosed. The method includes introducing the reactant gases argon and silane into a deposition chamber and enabling and disabling a plasma at various times during the deposition process.... | 10/29/2002 |
| 6465840 | Integrated structure comprising a patterned feature substantially of single grain polysilicon The electrical performance of a dielectric film for capacitive coupling in an integrated structure is enhanced by forming the polycrystalline electrically conductive layer coupled with the dielectric film substantially unigranular over the coupling area, ... | 10/15/2002 |
| 6459116 | Capacitor structure The present invention is directed to fabrication of a capacitor formed with a substantially concave shape and having optional folded or convoluted surfaces. The concave shape optimizes surface area within a small volume and thereby enables the capacitor t... | 10/01/2002 |
| 6451667 | Self-aligned double-sided vertical MIMcap A vertical MIM capacitor (140) including a first conductive line (124) and second conductive line (136) sandwiched around a vertical portion of a capacitor dielectric (134). Additional conductive lines (136) may be positioned vertically proximate first co... | 09/17/2002 |
| 6440825 | Method of controlling outdiffusion in a doped three-dimensional film A solid state fabrication technique for controlling the amount of outdiffusion from a three-dimensional film is comprised of the step of providing a first layer of insitu doped film in a manner to define an upper portion and a lower portion. A second laye... | 08/27/2002 |
| 6429071 | Method of increasing capacitance of memory cells incorporating hemispherical grained silicon Disclosed is a method of increasing capacitance of a memory cell capacitor. A bottom electrode, comprising a hemispherical grained (HSG) silicon layer, is subjected to a dry etch process. The etch tends to separate the individual grains of the HSG silicon... | 08/06/2002 |
| 6413831 | Method of fabrication for a honeycomb capacitor A honeycomb/webbed, high surface area capacitor formed by etching a storage poly using an etch mask having a plurality, of micro vias. The etch mask is preferably formed by applying an HSG polysilicon layer on a surface of the storage poly with a mask lay... | 07/02/2002 |
| 6410955 | Comb-shaped capacitor for use in integrated circuits A capacitor for use in integrated circuits comprises a layer of conductive material. The layer of conductive material including at least a first portion and a second portion, wherein the first portion and the second portion are arranged in a predetermined... | 06/25/2002 |
| 6410397 | Method for manufacturing a dielectric trench capacitor with a stacked-layer structure A trench is formed by forming a photoresist film on a second interlevel insulator and performing isoprotonic etching using the photoresist film as a mask. A lower electrode layer made of platinum (Pt), a dielectric film made of a dielectric material and a... | 06/25/2002 |
| 6404002 | Dynamic random access memory device with shaped storage nodes A DRAM device with increased surface area includes a pair of storage nodes arranged in a square configuration, and the square configurations are repeatedly arranged to form matrix cell array region. One of the storage node exhibits an "L" shaped pole and ... | 06/11/2002 |
| 6403444 | Method for forming storage capacitor having undulated lower electrode for a semiconductor device This invention provides a capacitor including a metal lower electrode having an undulated shape and an improved electrode area, and a method of manufacturing the same. A capacitor for data storage is formed on a semiconductor substrate (not shown) via an ... | 06/11/2002 |
| 6399490 | Highly conformal titanium nitride deposition process for high aspect ratio structures Process for forming highly conformal titanium nitride on a silicon substrate. A gaseous reaction mixture of titanium tetrachloride and ammonia is passed over the semiconductor substrate surface maintained at a temperature of about 350° C. to about 800° ... | 06/04/2002 |
