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| Number | Title | Issue Date |
| 7339230 | Structure and method for making high density mosfet circuits with different height contact lines Embodiments herein present a structure, method, etc. for making high density MOSFET circuits with different height contact lines. The MOSFET circuits include a contact line, a first gate layer situated proximate the contact line, and at least one subsequent gate lay... | 03/04/2008 |
| 7170175 | Semiconductor device and production method thereof A semiconductor device and a production method thereof capable of reducing warps of a semiconductor wafer when packaging at a wafer level in a SiP type semiconductor device, is configured that an insulating layer is formed by stacking a plurality of resin layers on ... | 01/30/2007 |
| 6949839 | Aligned buried structures formed by surface transformation of empty spaces in solid state materials A method of aligning a plurality of empty-spaced buried patterns formed in semiconductor monocrystalline substrates is disclosed. In an exemplary embodiment, high-temperature metal marks are formed to include a conductive material having a melting temperature higher... | 09/27/2005 |
| 6885078 | Circuit isolation utilizing MeV implantation A circuit isolation technique that uses implanted ions in embedded portions of a wafer substrate to lower the resistance of the substrate under circuits formed on the wafer or portions of circuits formed on the wafer to prevent the flow of injected currents across t... | 04/26/2005 |
| 6885044 | Arrays of nonvolatile memory cells wherein each cell has two conductive floating gates In a nonvolatile memory array in which each cell (110) has two floating gates (160), for any two consecutive memory cells, one source/drain region (174) of one of the cells and one source/drain region of the other one of the cells are provided b... | 04/26/2005 |
| 6861705 | Driver circuits and methods for manufacturing driver circuits Embodiments include a driver circuit that is suitable to prevent a delay in responding to an input of a drive signal and a method for manufacturing the same. Three contact holes are provided for each of the transistors Tr1-Tr4 for connecting th... | 03/01/2005 |
| 6844629 | Display panel with bypassing lines A display panel comprises the following elements. A pixel array arranged by a plurality of pixel devices is applied for producing images according to input signals. A plurality of COG chips are fabricated on a peripheral region of the display panel and connected in ... | 01/18/2005 |
| 6841408 | Method of alignment for buried structures formed by surface transformation of empty spaces in solid state materials A method of aligning a plurality of empty-spaced buried patterns formed in semiconductor monocrystalline substrates is disclosed. In an exemplary embodiment, high-temperature metal marks are formed to include a conductive material having a melting temperature higher... | 01/11/2005 |
| 6822329 | Integrated circuit connecting pad Each connecting pad includes a continuous top metal layer on the top metallization level and having on its top face an area for welding a connecting wire. Also, the pad has a reinforcing structure under the welding area and includes at least one discontinuous metal ... | 11/23/2004 |
| 6579738 | Method of alignment for buried structures formed by surface transformation of empty spaces in solid state materials A method of aligning a plurality of empty-spaced buried patterns formed in semiconductor monocrystalline substrates is disclosed. In an exemplary embodiment, high-temperature metal marks are formed to include a conductive material having a melting tempera... | 06/17/2003 |
| 6531755 | Semiconductor device and manufacturing method thereof for realizing high packaging density In a semiconductor device in which an interlayer insulating layer is formed of a low density material (porous silica etc.) and a hole or a trench is formed in the interlayer insulating layer by processing the interlayer insulating layer and an electricall... | 03/11/2003 |
| 6498384 | Structure and method of semiconductor via testing A semiconductor wafer having a via test structure is provided which includes a semiconductor substrate having a plurality of semiconductor devices. A dielectric layer deposited over the semiconductor substrate has second and fourth channels unconnected to... | 12/24/2002 |
| 6492736 | Power mesh bridge A multiple layer mesh design that provides that a bridge associated with a second layer connects a rail on a first layer to a trunk on a fourth layer. If the trunk on the third layer shadows a plurality of rails on the first layer, preferably the bridge i... | 12/10/2002 |
| 6469360 | Integrated circuit devices providing reduced electric fields during fabrication thereof A method for fabricating an integrated circuit device includes the steps of forming first and second conductive regions on a substrate. The second conductive region is divided into first and second subregions wherein the first subregion is adjacent the fi... | 10/22/2002 |
| 6455885 | Inductor structure for high performance system-on-chip using post passivation process The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of pol... | 09/24/2002 |
| 6348723 | Semiconductor device with a dummy wire positioned to prevent charging/discharging of the parasitic capacitance of a signal wire A semiconductor device according to the present invention includes: a semiconductor substrate; a signal wire, disposed on the semiconductor substrate, for transmitting a signal between circuits; and a dummy wire disposed between the signal wire and the re... | 02/19/2002 |
| 6320262 | Semiconductor device and manufacturing method thereof The present invention aims at improving the lifetime of the wiring connecting to the hole nearest to the bonding pad and thereby improving the reliability of the semiconductor device. The invention relates to such semiconductor device and method of manufa... | 11/20/2001 |
| 6303983 | Apparatus for manufacturing resin-encapsulated semiconductor devices A semiconductor device includes a lead frame, a semiconductor chip, a resin-encapsulated portion, and tie bars. The semiconductor chip is mounted on a die pad of the lead frame. The resin-encapsulated portion resin-encapsulates the semiconductor chip. The... | 10/16/2001 |
| 6215077 | Thin-film laminate type conductor A thin-film laminate type conductor is provided which includes a first conductor that is a metal thin film formed of Al or Al alloy, and a second conductor that is a transparent conductive thin film formed of a metal oxide. The first and second conductors... | 04/10/2001 |
| 6177716 | Low loss capacitor structure A capacitor structure (100) including first and second capacitor plates (102, 106) insulatingly spaced from each other by a capacitor dielectric (102). A first set of conductive posts (301) electrically couple to the first capacitor plate (102) and extend... | 01/23/2001 |
| 6114767 | EEPROM semiconductor device and method of fabricating the same There is provided an EEPROM semiconductor device including (a) a plurality of field insulating films each extending perpendicularly to word lines, (b) a plurality of memory cells arranged in a matrix, each memory cell having a floating gate, a control gat... | 09/05/2000 |
| 6020612 | Semiconductor integrated circuit having efficient layout of wiring lines A semiconductor integrated circuit includes a gate extending in a first direction, a diffusion-layer region corresponding to the gate, and a plurality of backing wiring lines connected to the diffusion-layer region and extending in a first wiring layer in... | 02/01/2000 |
| 5945717 | Segmented non-volatile memory array having multiple sources An arrangement of non-volatile memory cells, such as flash memory cells which includes erase blocks which can be separately erased and which require a reduced amount of circuit area. The erase blocks each include an array of the cells arranged in rows and... | 08/31/1999 |
| 5854515 | Integrated circuit having conductors of enhanced cross-sectional area A interconnect structure is provided having a conductor with enhanced thickness. The conductor includes an upper portion and a lower portion, wherein the lower portion geometry is sufficient to increase the current-carrying capacity beyond that provided b... | 12/29/1998 |
| 5838032 | Precision capacitor array Capacitor arrays may be incorporated within silicon integrated circuits as part of analog-to-digital or digital-to-analog converters. Capacitance ratios between individual capacitors need to be controlled to better than 1%. Because of microloading effects... | 11/17/1998 |
| 5789791 | Multi-finger MOS transistor with reduced gate resistance The gate resistance of a high-frequency multi-finger MOS transistor is reduced by shorting together the ends of each of the gates by utilizing gate contacts, metal regions, vias, and a metal layer. Alternately, the gate resistance is reduced by utilizing ... | 08/04/1998 |
| 5760476 | Interconnect run between a first point and a second point in a semiconductor device for reducing electromigration failure In a first approach, an interconnect structure (10) reduces peak localized interconnect current density by distributing current flow around the perimeter (22) of an interlevel connector (14) in a semiconductor device. A first interconnect level (12) is co... | 06/02/1998 |
| 5635767 | Semiconductor device having built-in high frequency bypass capacitor A high frequency bypass capacitor (36, 36') is built into a thin-film portion (16, 16') of a polymer carrier substrate (15) of a PBGA (10). The carrier substrate (15) has both a stiffener (18) and a thin-film portion (16, 16') which has multiple metal lay... | 06/03/1997 |
| 5600168 | Semiconductor element and method for fabricating the same This invention relates to MOS transistors and a method for fabricating the MOS transistors having LDD (Lightly Doped Drain) structures, which comprises a first conduction type semiconductor substrate, a second conduction type high density source and drain... | 02/04/1997 |
| 5594281 | Semiconductor apparatus having wiring structure of an integrated circuit in which a plurality of logic circuits of the same structure are arranged in the same direction In a semiconductor apparatus, a first circuit provided on a major surface of a semiconductor substrate. The first circuit includes a plurality of logic circuits of an identical structure, the logic circuits having input terminals supplied with identical s... | 01/14/1997 |
| 5559345 | Thin film transistor having redundant metal patterns There is disclosed an LCD element which prevents delamination of a main data line and a redundancy line caused by the stress therebetween and breaking of the data line. It comprises a partially patterned redundancy line which reinforces a data line to pre... | 09/24/1996 |
| 5528082 | Thin-film structure with tapered feature A feature in a thin-film structure such as an AMLCD array has an edge with a tapered sidewall profile, reducing step coverage problems. The feature can be produced by producing a layer in which local etch rates vary in the thickness direction of the layer... | 06/18/1996 |
| 5491352 | Semiconductor device having peripheral metal wiring At a peripheral area of a semiconductor chip where active elements are not formed, a layer underlying a power supply wiring or ground wiring is provided with an uneven surface. The uneven or corrugated surface at the interface between the wiring and the u... | 02/13/1996 |
| 5477085 | Bonding structure of dielectric substrates for impedance matching circuits on a packaging substrate involved in microwave integrated circuits The present invention provides a bonding structure between a dielectric substrate made of a dielectric material and a packaging substrate made of a heat conductive material involved in microwave integrated circuits. Both the dielectric and heat conductive... | 12/19/1995 |
| 5461260 | Semiconductor device interconnect layout structure for reducing premature electromigration failure due to high localized current density In a first approach, an interconnect structure (10) reduces peak localized interconnect current density by distributing current flow around the perimeter (22) of an interlevel connector (14) in a semiconductor device. A first interconnect level (12) is co... | 10/24/1995 |
| 5455456 | Integrated circuit package lid A novel lid for sealing an encapsulant within a cavity of an integrated circuit package is disclosed herein. A ring is formed around a cavity opening, where a semiconductor die is located in an integrated circuit package. A lid, having a radially extendin... | 10/03/1995 |
| 5391920 | Semiconductor device having peripheral metal wiring At a peripheral area of a semiconductor chip where active elements are not formed, a layer underlying a power supply wiring or ground wiring is provided with an uneven surface. The uneven or corrugated surface at the interface between the wiring and the u... | 02/21/1995 |
| 5309015 | Clock wiring and semiconductor integrated circuit device having the same In a clock wiring of a semiconductor integrated circuit device or a printed wiring, a shield clock wiring to be connected with the same drive source as a drive source to be connected with the clock wiring is laid adjacent to the whole or partial length of... | 05/03/1994 |
| 5300814 | Semiconductor device having a semiconductor substrate with reduced step between memory cells A semiconductor device comprising a semiconductor substrate, a plurality of memory cell regions each having a plurality of memory cells disposed on the semiconductor substrate, a word line formed in a first level above the semiconductor substrate, a bit l... | 04/05/1994 |
| 5274264 | Defect tolerant power distribution network and method for integrated circuits Short circuits in the power distribution network of a circuit structure are accurately located and isolated by providing selected power distribution lines with areas whose width is reduced sufficiently to produce a highly resolved current-induced hot spot... | 12/28/1993 |
