Did You Know...
...that Charles Goodyear performed some of his experiments on rubber while in debtor's prison? He was there so often he referred to it as his "hotel". Chronically in debt because of poor business sense and ill health, Goodyear depended on the generosity of friends and family. Even after he unlocked the secret to vulcanizing rubber, he was unable to improve his financial situation. When he died, his estate was $200,000 in debt.
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| Number | Title | Issue Date |
| 7432562 | SRAM devices, and electronic systems comprising SRAM devices The invention includes SRAM constructions comprising at least one transistor device having an active region extending into a crystalline layer comprising Si/Ge. A majority of the active region within the crystalline layer is within a single crystal of the crystallin... | 10/07/2008 |
| 7432555 | Testable electrostatic discharge protection circuits A semiconductor die has a bonding pad for a MOSFET such as a power MOSFET and a separate bonding pad for ESD protection circuitry. Connecting the bonding pads together makes the ESD protection circuitry functional to protect the MOSFET. Before connecting the bonding... | 10/07/2008 |
| 7375401 | Static random access memory using thin film transistors A semiconductor thin film is formed having a lateral growth region which is a collection of columnar or needle-like crystals extending generally parallel with a substrate. The semiconductor thin film is illuminated with laser light or strong light having equivalent ... | 05/20/2008 |
| 7355240 | Semiconductor product including logic, non-volatile memory and volatile memory devices and method for fabrication thereof A semiconductor product and a method for fabricating the semiconductor product employ a semiconductor substrate. The semiconductor substrate has a logic region having a logic device formed therein, a non-volatile memory region having a non-volatile memory device for... | 04/08/2008 |
| 7319254 | Semiconductor memory device having resistor and method of fabricating the same A semiconductor device having resistors in a peripheral area and fabrication method thereof are provided. A mold layer is formed on a semiconductor substrate. The mold layer is patterned to form first molding holes and a second molding hole in the mold layer. A stor... | 01/15/2008 |
| 7304352 | Alignment insensitive D-cache cell A D-Cache SRAM cell having a modified design in schematic and layout that exhibits increased symmetry from the circuit schematic and the physical cell layout perspectives. That is, the SRAM cell includes two read ports and minimizes asymmetry by provisioning one rea... | 12/04/2007 |
| 7292469 | Methods of programming non-volatile memory devices including transition metal oxide layer as data storage material layer and devices so operated A method of programming a non-volatile memory device including a transition metal oxide layer includes applying a first electric pulse to the transition metal oxide layer for a first period to reduce a resistance of the transition metal oxide layer and applying a se... | 11/06/2007 |
| 7271454 | Semiconductor memory device and method of manufacturing the same A contact connected to a word line is formed on a gate electrode of an access transistor of an SRAM cell. The contact passes through an element isolation insulating film to reach an SOI layer. A body region of a driver transistor and that of the access transistor ar... | 09/18/2007 |
| 7259431 | Static random access memory using thin film transistors A semiconductor thin film is formed having a lateral growth region which is a collection of columnar or needle-like crystals extending generally parallel with a substrate. The semiconductor thin film is illuminated with laser light or strong light having equivalent ... | 08/21/2007 |
| 7256463 | Semiconductor device having SOI structure including a load resistor of an sram memory cell It is an object to provide a semiconductor device having an SOI structure in which an electric potential of a body region in an element formation region isolated by a partial isolation region can be fixed with a high stability. A MOS transistor comprising a source r... | 08/14/2007 |
| 7224232 | RF power amplifier and method for packaging the same A method and apparatus is provided for use in power amplifiers for reducing the peak voltage that transistors are subjected to. A power amplifier is provided with first and second switching devices and an inductor connected between the switching devices. The switchi... | 05/29/2007 |
| 7208369 | Dual poly layer and method of manufacture Semiconductor devices having a dual polysilicon electrode and a method of manufacturing are provided. The semiconductor devices include a first polysilicon layer deposited on a second polysilicon layer. Each polysilicon layer may be doped individually. The method al... | 04/24/2007 |
| 7208794 | High-density NROM-FINFET Semiconductor memory having memory cells, each including first and second conductively-doped contact regions and a channel region arranged between the latter, formed in a web-like rib made of semiconductor material and arranged one behind the other in this sequence ... | 04/24/2007 |
| 7208814 | Resistive device and method for its production A resistive device includes a resistive region of a semiconductor material that includes a first region and a second region, wherein the first region has a higher dopant concentration than the second region, and wherein a resistance-determining width of a current pa... | 04/24/2007 |
| 7166904 | Structure and method for local resistor element in integrated circuit technology A method and system for forming a semiconductor device having superior ESD protection characteristics. A resistive material layer is disposed within a contact hole on at least one of the contact stud upper and lower surface. In preferred embodiments, the integral re... | 01/23/2007 |
| 7161404 | Single event upset hardened latch A hardened latch capable of providing protection against single event upsets (SEUs) is disclosed. The hardened latch includes a first latch and a second latch that mirrors a subset of gates of the first latch. The second latch is inserted in the feedback path of the... | 01/09/2007 |
| 7154161 | Composite ground shield for passive components in a semiconductor die According to one exemplary embodiment, a structure situated in a semiconductor die comprises an active shield situated in a substrate, where the active shield comprises a salicide layer situated on an active region, and where the active shield has a first conductivi... | 12/26/2006 |
| 7123504 | Semiconductor integrated circuit device having static random access memory mounted thereon A semiconductor integrated circuit device is configured by eight transistors including the six transistors configuring the data holding section and the two NMOS transistors configuring the reading stage. The threshold voltage of the NMOS transistors configuring the ... | 10/17/2006 |
| 7110283 | Semiconductor memory device and semiconductor integrated circuit In a semiconductor memory device, third and fourth transistors are configured as a vertical structure. The third transistor is laminated over a first transistor, and the fourth transistor is laminated over a second transistor, whereby a reduction in cell area is ach... | 09/19/2006 |
| 7092273 | Low voltage non-volatile memory transistor A p-channel non-volatile memory (NVM) transistor is programmed by shifting the threshold voltage of the transistor. The threshold voltage is shifted by introducing a programming current to the gate electrode of the transistor, and simultaneously introducing a negati... | 08/15/2006 |
| 7078774 | Semiconductor memory device having a shallow trench isolation structure A semiconductor memory device includes a cell array having matrix-like arrayed plural SRAMs on a semiconductor substrate having an N-well and P-well. The N-well and the P-well are isolated from each other with an isolation region each having a shallow trench structu... | 07/18/2006 |
| 7075167 | Spiral inductor formed in a semiconductor substrate An inductor formed on a semiconductor substrate, comprising active device regions. The inductor comprises conductive lines formed on a dielectric layer overlying the semiconductor substrate. The conductive lines are patterned and etched into the desired shape, in on... | 07/11/2006 |
| 7064398 | Semiconductor memory device In a full CMOS SRAM having a lateral type cell (memory cell having three partitioned wells arranged side by side in a word line extending direction and longer in the word line direction than in the bit line direction) including first and second driver MOS transistor... | 06/20/2006 |
| 7061128 | Semiconductor device and manufacturing method of the same A semiconductor device according to the present invention includes: a semiconductor substrate including an active region and an isolation region; a gate electrode formed on the active region with an oxide film interposed therebetween; and a set of impurity regions f... | 06/13/2006 |
| 7050319 | Memory architecture and method of manufacture and operation thereof An architecture, and its method of formation and operation, containing a high density memory array of semi-volatile or non-volatile memory elements, including, but not limited to, programmable conductive access memory elements. The architecture in one exemplary embo... | 05/23/2006 |
| 7045864 | Semiconductor integrated circuit device A semiconductor integrated circuit device, e.g., a memory cell of an SRAM, is formed of a pair of inverters having their input and output points connected in a crisscross manner and being formed of drive n-channel MISFETs and load p-channel MISFETs. The n-channel MI... | 05/16/2006 |
| 7042107 | Scalable two transistor memory devices A memory device includes a semiconductor substrate, a first gate insulator on a first portion of a semiconductor substrate, a storage node on the first gate insulator, a tunnel junction barrier on the storage node and a data electrode on the layer tunnel junction ba... | 05/09/2006 |
| 7038297 | Semiconductor diffused resistors with optimized temperature dependence Ion implanted resistors formed in the body of a crystalline silicon substrate. The resistors have a different conductivity type from that of the silicon substrate. The sheet resistance and temperature dependence of the resistor layer is determined by the dose of the... | 05/02/2006 |
| 7026692 | Low voltage non-volatile memory transistor A p-channel non-volatile memory (NVM) transistor is programmed by shifting the threshold voltage of the transistor. The threshold voltage is shifted by introducing a programming current to the gate electrode of the transistor, and simultaneously introducing a negati... | 04/11/2006 |
| 7022579 | Method for filling via with metal A method of filling vias for a PCRAM cell with a metal is described. A PCRAM intermediate structure including a substrate, a first conductor, and an insulator through which a via extends has a metallic material formed within the via and on a surface of the insulator... | 04/04/2006 |
| 7005691 | Magnetoresistance element and magnetoresistance storage element and magnetic memory A magnetoresistance element, wherein a first electric conductor is so formed as to contact almost the center of the surface opposite to a non-magnetic layer of a first ferromagnetic layer so formed as to sandwich, along with a second ferromagnetic layer, the non-mag... | 02/28/2006 |
| 7002258 | Dual port memory core cell architecture with matched bit line capacitances A Static Random Access Memory (SRAM) dual port memory with an improved core cell design having internally matched capacitances and decreased bit line capacitance is disclosed. The core cell is fabricated on a substrate divided into three approximately equal columns ... | 02/21/2006 |
| 6998306 | Semiconductor memory device having a multiple tunnel junction pattern and method of fabricating the same The present invention discloses a semiconductor memory device having a multiple tunnel junction pattern and a method of forming the same. The semiconductor memory device includes a unit cell composed of planar transistor and vertical transistors. The planar transist... | 02/14/2006 |
| 6984859 | Semiconductor memory device with static memory cells An access transistor, provided between a storage node in a memory cell and a bit line is formed of a P channel MOS transistor including P type first and second impurity regions formed in an N type well and a gate electrode. Buried interconnection is formed of metal ... | 01/10/2006 |
| 6930344 | Nonvolatile semiconductor memory device with stable ferroelectric capacitor A nonvolatile semiconductor memory device includes a substrate, a plurality of transistors formed on the substrate to constitute a latch, a plate line, and a pair of capacitors each including a lower electrode, a ferroelectric film, and an upper electrode, the pair ... | 08/16/2005 |
| 6924560 | Compact SRAM cell with FinFET A method and system is disclosed for an SRAM device cell having at least one device of a first semiconductor type and at lease one device of a second semiconductor type. The cell has a first device of the first type constructed as a part of a first FinFET having one... | 08/02/2005 |
| 6921959 | Semiconductor device A semiconductor device includes a semiconductor substrate, an insulating layer, an inductor, a guard ring and a potential-applying line. The insulating layer is formed on the semiconductor substrate. The inductor is formed on the insulating layer. The guard ring is ... | 07/26/2005 |
| 6864506 | SRAM cell and method for fabricating the same SRAM cell and method for fabricating the same, the SRAM cell including a first local interconnection connected between first terminals of the first access transistor, the first load transistor, and the first drive transistor, and gates of the second load transistor,... | 03/08/2005 |
| 6815839 | Soft error resistant semiconductor memory device The semiconductor memory device includes two PMOS transistors that make the SRAM memory cell. The gate insulating films of these PMOS transistors are formed using a material that has a high permittivity. As a result, the capacitance of memory nodes is increased, and... | 11/09/2004 |
| 6812574 | Semiconductor storage device and method of fabricating the same A semiconductor storage device includes a memory cell array, a plurality of word lines, a plurality of bit lines, a first gate wiring element 3a, 3b, a second gate wiring element 3c, 3d, a first connector 5 | 11/02/2004 |
