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| Number | Title | Issue Date |
| 7772711 | Semiconductor device including single crystal silicon layer A semiconductor device including a substrate, a P-MOS single crystal TFT formed on the substrate, and an N-MOS single crystal TFT formed on the P-MOS single crystal TFT. The source region of the P-MOS single crystal TFT and the source region of the N-MOS single crys... | 08/10/2010 |
| 7436078 | Line layout structure of semiconductor memory device An apparatus including a trolling motor having at least one operational subsystem and the trolling motor also having an integral electronic controller for controlling the operational subsystem wherein the improvement comprises an integral electronic diagnostic syste... | 10/14/2008 |
| 7432562 | SRAM devices, and electronic systems comprising SRAM devices The invention includes SRAM constructions comprising at least one transistor device having an active region extending into a crystalline layer comprising Si/Ge. A majority of the active region within the crystalline layer is within a single crystal of the crystallin... | 10/07/2008 |
| 7425744 | Fabricating logic and memory elements using multiple gate layers Various embodiments are directed to different methods and systems relating to design and implementation of memory cells such as, for example, static random access memory (SRAM) cells. In one embodiment, a memory cell may include a first layer of conductive material ... | 09/16/2008 |
| 7411256 | Semiconductor integrated circuit device capacitive node interconnect A semiconductor integrated circuit device is provided, which involves inhibiting a pattern change in the node interconnect and an increase of number of manufacturing process, when the capacitor is additionally installed in the SRAM, while providing higher reliabilit... | 08/12/2008 |
| 7405447 | Silicon rich barrier layers for integrated circuit devices Semiconductor devices and memory cells are formed using silicon rich barrier layers to prevent diffusion of dopants from differently doped polysilicon films to overlying conductive layers or to substrates. A polycilicide gate electrode structure may be formed using ... | 07/29/2008 |
| 7397693 | Semiconductor memory device with memory cells operated by boosted voltage A memory using an SRAM memory cell intended for low-voltage operation is designed to decrease the threshold value of MOS transistors constituting the memory cell without substantial decrease in the static noise margin, which is the operational margin of the memory c... | 07/08/2008 |
| 7397691 | Static random access memory cell with improved stability A memory cell comprises a wordline, a first digital inverter with a first input and a first output, and a second digital inverter with a second input and a second output. Moreover, the memory cell further comprises a first feedback connection connecting the first ou... | 07/08/2008 |
| 7388267 | Selective stress engineering for SRAM stability improvement An integrated circuit (IC) structure including a SRAM cell is provided in which the performance of the pass-gate transistors is degraded in order to increase the beta ratio of the transistors within the SRAM cell. In particular, the increased beta ratio is obtained ... | 06/17/2008 |
| 7382026 | Semiconductor memory device and method of manufacturing the same A contact connected to a word line is formed on a gate electrode of an access transistor of an SRAM cell. The contact passes through an element isolation insulating film to reach an SOI layer. A body region of a driver transistor and that of the access transistor ar... | 06/03/2008 |
| 7361960 | Semiconductor device and method of manufacturing the same A first insulator film and a first polysilicon film are formed on first and second element regions of a semiconductor substrate. The first insulator film and first polysilicon film are removed from the second element region. A second insulator film is formed on the ... | 04/22/2008 |
| 7361961 | Method and apparatus with varying gate oxide thickness An integrated circuit having an enhanced on-off swing for pass gate transistors is provided. The integrated circuit includes a core region that includes core transistors and pass gate transistors. The core transistors have a gate oxide associated with a first thickn... | 04/22/2008 |
| 7358556 | SRAM cell structure and manufacturing method thereof A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an openi... | 04/15/2008 |
| 7358575 | Method of fabricating SRAM device A method of fabricating an SRAM device is provided, by which a junction node area is stably secured in a 1T type SRAM device. The method includes forming first and second conductor patterns on a cell area of a semiconductor substrate and a third conductor pattern on... | 04/15/2008 |
| 7355880 | Soft error resistant memory cell and method of manufacture A semiconductor device memory cell (100) can include a built-in capacitor for reducing a soft-error rate (SER). A memory cell (100) can include a first inverter (102) and second inverter (104) arranged in a cross-coupled configuration. A ... | 04/08/2008 |
| 7348658 | Multilayer silicon over insulator device An apparatus and method for a multilayer silicon over insulator (SOI) device is provided. In the multilayer SOI device, the crystal orientation of at least one active region of a device is different than the active region of at least another device. Where the multil... | 03/25/2008 |
| 7348640 | Memory device A memory capable of reducing the memory cell size is provided. In this memory, a first gate electrode of a first selection transistor and a second gate electrode of a second selection transistor are provided integrally with a word line, and arranged to obliquely ext... | 03/25/2008 |
| 7341901 | Semiconductor processing methods of forming integrated circuitry Semiconductor processing methods of forming integrated circuitry are described. In one embodiment, memory circuitry and peripheral circuitry are formed over a substrate. The peripheral circuitry comprises first and second type MOS transistors. Second type halo impla... | 03/11/2008 |
| 7333380 | SRAM memory device with flash clear and corresponding flash clear method A static memory device includes at least one memory cell with two cross-coupled CMOS inverters to be connected to first and second voltages. The substrate of the NMOS transistor of a first CMOS inverter is electrically insulated from the substrate of the NMOS transi... | 02/19/2008 |
| 7332780 | Inverter, semiconductor logic circuit, static random access memory and data latch circuit A dual structure is introduced to the transistor in a flip-flop or a data input step controlled by a clock of a semiconductor logic circuit. The dual structure is formed by connecting a transistor with a MOS transistor having a channel of the same conductivity type ... | 02/19/2008 |
| 7321504 | Static random access memory cell A static random access memory (SRAM) cell having an inverter and a tri-state inverter. An input of the inverter is coupled to an output of the tri-state inverter and an output of the inverter is coupled to an input of the tri-state inverter. The tri-state inverter h... | 01/22/2008 |
| 7319611 | Bitline transistor architecture for flash memory A memory array includes a buried diffusion region, a first source line that supplies electrical power to the buried diffusion region, a second source line that supplies electrical power to the buried diffusion region, a first bitline transistor having a first channe... | 01/15/2008 |
| 7312486 | Stripe board dummy metal for reducing coupling capacitance Dishing is known to be a problem after CMP of dielectric layers in which the distribution of embedded metal is non-uniform. This problem has been solved by populating those areas where the density of embedded metal is low with unconnected regions that, instead of be... | 12/25/2007 |
| 7309890 | SRAM cell structure and manufacturing method thereof A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an openi... | 12/18/2007 |
| 7304352 | Alignment insensitive D-cache cell A D-Cache SRAM cell having a modified design in schematic and layout that exhibits increased symmetry from the circuit schematic and the physical cell layout perspectives. That is, the SRAM cell includes two read ports and minimizes asymmetry by provisioning one rea... | 12/04/2007 |
| 7301797 | Method of operating semiconductor integrated circuit including SRAM block and semiconductor integrated circuit including SRAM block A method of operating a semiconductor integrated circuit including a SRAM block, in which non-volatile data is stored in the SRAM block, is disclosed. In an exemplary embodiment, the non-volatile data is stored by flowing a drain current in one of a pair of pull-dow... | 11/27/2007 |
| 7294889 | Semiconductor device having a well structure for improving soft error rate immunity and latch-up immunity and a method of making such a device A semiconductor device with improved soft error rate immunity and latch-up immunity and a method of forming the same. The device includes first wells of first conductivity type and second well of second conductivity type formed in the semiconductor substrate of firs... | 11/13/2007 |
| 7291889 | Basic cells configurable into different types of semiconductor integrated circuits The basic cell constituted by a semiconductor integrated circuit comprises two PMOS transistors and two NMOS transistors. By setting the gate widths of the gates of these transistors to prescribed lengths, the efficiency of use of elements within the basic cell is i... | 11/06/2007 |
| 7291880 | Transistor assembly Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry are described. In one embodiment, active areas are formed over a substrate, with one of the ... | 11/06/2007 |
| 7286389 | Low-power, p-channel enhancement-type metal-oxide semiconductor field-effect transistor (PMOSFET) SRAM cells Low-power, all-p-channel enhancement-type metal-oxide semiconductor field-effect transistor (PMOSFET) SRAM cells are disclosed. A PMOSFET SRAM cell is disclosed. The SRAM cell can include a latch having first and second PMOSFETs for storing data. Further, a gate of ... | 10/23/2007 |
| 7285832 | Multiport single transistor bit cell A multiport memory cell (200, 300, 600) includes a first word line (WL1) coupled to a gate electrode of a first transistor (201, 301, 601). A second word line (WL2) is coupled to a gate electrode of a second transistor (202, 302, 602 | 10/23/2007 |
| 7279194 | Thin film formation apparatus and method of manufacturing self-light-emitting device using thin film formation apparatus A means of effectively applying an organic EL material application liquid with good application liquid cut-off is provided. A heater and an ultrasonic oscillator are formed in a thin film formation apparatus when applying the application liquid, and heat and ultraso... | 10/09/2007 |
| 7279755 | SRAM cell with improved layout designs A 6T SRAM cell includes a first inverter having a first pull-up transistor and a first pull-down transistor serially coupled between a supply source and a complementary supply source, and a second inverter cross-coupled with the first inverter having a second pull-u... | 10/09/2007 |
| 7271454 | Semiconductor memory device and method of manufacturing the same A contact connected to a word line is formed on a gate electrode of an access transistor of an SRAM cell. The contact passes through an element isolation insulating film to reach an SOI layer. A body region of a driver transistor and that of the access transistor ar... | 09/18/2007 |
| 7271451 | Memory cell structure A memory structure that reduces soft-errors for us in CMOS devices is provided. The memory cell layout utilizes transistors oriented such that the source-to-drain axis is parallel a shorted side of the memory cell. The dimensions of the memory cell are such that it ... | 09/18/2007 |
| 7269056 | Power grid design for split-word line style memory cell Disclosed is an improved power grid design for split-word line style memory cell. An array of memory cells comprises a first metal layer for local interconnections; a second metal layer for a bit line, a complementary bit line, and a first voltage line located betwe... | 09/11/2007 |
| 7269057 | Method for connecting circuit elements within an integrated circuit for reducing single-event upsets A method for connecting circuit elements within an integrated circuit for reducing single-event upsets is disclosed. The integrated circuit includes a first and second circuit elements that are substantially identical to each other. In order to reduce the single-eve... | 09/11/2007 |
| 7256455 | Double gate semiconductor device having a metal gate A semiconductor device may include a substrate, an insulating layer formed on the substrate and a conductive fin formed on the insulating layer. The conductive fin may include a number of side surfaces and a top surface. The semiconductor device may also include a s... | 08/14/2007 |
| 7250661 | Semiconductor memory device with plural source/drain regions A semiconductor memory device includes first and second source/drain regions, and first and second semiconductor regions. The first source/drain region of a first conductive type is formed in a first well region of a second conductive type for a pair of first MIS-ty... | 07/31/2007 |
| 7250657 | Layout structure for memory arrays with SOI devices A layout structure of a static random access memory (SRAM) cell array includes at least one SRAM cell area, oxide defined (OD) area and strapping cell area. The SRAM cell area has a longitudinal side being at least twice longer than a transverse side thereof. The ox... | 07/31/2007 |
