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| Number | Title | Issue Date |
| 7342291 | Standby current reduction over a process window with a trimmable well bias An integrated circuit device including a plurality of MOSFETs of similar type and geometry is formed on a substrate with an ohmic contact, and an adjustable voltage source on the die utilizing clearable fuses is coupled between the ohmic contact and the sources of t... | 03/11/2008 |
| 7333380 | SRAM memory device with flash clear and corresponding flash clear method A static memory device includes at least one memory cell with two cross-coupled CMOS inverters to be connected to first and second voltages. The substrate of the NMOS transistor of a first CMOS inverter is electrically insulated from the substrate of the NMOS transi... | 02/19/2008 |
| 7109558 | Power MOS transistor having capability for setting substrate potential independently of source potential A power MOS transistor formed of an array of source cells and drain cells on an IC chip substrate has a plurality of substrate contact cells, each formed external to the source cells, having respective substrate potential-setting electrodes to which an externally su... | 09/19/2006 |
| 6885054 | Threshold voltage stabilizer, method of manufacturing and integrated circuit employing the same The present invention provides a threshold voltage stabilizer for use with a MOS transistor having a body effect associated therewith. In one embodiment, the threshold voltage stabilizer, includes a body well located in a substrate, a source located in the body well... | 04/26/2005 |
| 6867494 | Semiconductor module A semiconductor module includes a supporting substrate having a connecting section on a first major surface thereof. A first semiconductor chip includes a first MIS transistor a source of which is formed on the bottom thereof. A second semiconductor chip includes a ... | 03/15/2005 |
| 6864539 | Semiconductor integrated circuit device having body biasing circuit for generating forward well bias voltage of suitable level by using simple circuitry A semiconductor integrated circuit device has a MISFET and a body biasing circuit. The MISFET has a source electrode and a drain electrode of a first conductivity type and a gate electrode, and the MISFET is formed in a well of a second conductivity type. The body b... | 03/08/2005 |
| 6849909 | Method and apparatus for weak inversion mode MOS decoupling capacitor A method and apparatus for providing a weak inversion mode metal-oxide-semiconductor (MOS) decoupling capacitor is described. In one embodiment, an enhancement-mode p-channel MOS (PMOS) transistor is constructed with a gate material whose work function differs from ... | 02/01/2005 |
| 6809425 | Integrated circuit with a reprogrammable nonvolatile switch having a dynamic threshold voltage (VTH) for selectively connecting a source for a signal to a circuit A nonvolatile reprogrammable switch for use in a PLD or FPGA has a nonvolatile memory cell connected to the gate of an MOS transistor, which is in a well, with the terminals of the MOS transistor connected to the source of the signal and to the circuit. The nonvolat... | 10/26/2004 |
| 6794720 | Dynamic threshold voltage metal insulator field effect transistor In a semiconductor device in which the gate electrode of a MISFET formed on a semiconductor substrate is electrically connected to a well region under the channel of the MISFET, the MISFET is formed in an island-shaped element region formed on the semiconductor subs... | 09/21/2004 |
| 6713804 | TFT with a negative substrate bias that decreases in time A voltage applying section (32) is connected to a silicon substrate (1). Emission of radiation to a semiconductor device causes a large number of holes to accumulate within a BOX layer (2) in the vicinity of the interface with respect to a silic... | 03/30/2004 |
| 6693328 | Semiconductor device formed in a semiconductor layer provided on an insulating film A semiconductor device includes an insulating film provided on a semiconductor substrate and a semiconductor layer provided on the insulating film. An element separating insulating film separates element area. A first gate insulating film is provided on t... | 02/17/2004 |
| 6465852 | Silicon wafer including both bulk and SOI regions and method for forming same on a bulk silicon wafer A silicon substrate comprises a silicon-on-insulator (SOI) portion which includes an insulating silicon dioxide layer beneath a device layer. SOI circuit structures, including SOI field effect transistors, are formed in the device layer. The substrate als... | 10/15/2002 |
| 6465823 | Dynamic threshold voltage metal insulator semiconductor effect transistor In a semiconductor device in which the gate electrode of a MISFET formed on a semiconductor substrate is electrically connected to a well region under the channel of the MISFET, the MISFET is formed in an island-shaped element region formed on the semicon... | 10/15/2002 |
| 6404050 | Commonly housed diverse semiconductor A MOSFET die and a Schottky diode die are mounted on a common lead frame pad and their drain and cathode, respectively, are connected together at the pad. The pad has a plurality of pins extending from one side thereof. The lead frame has insulated pins o... | 06/11/2002 |
| 6398185 | Water flow timer A water flow timer including a main body, a water stopping membrane, a control rod, a bottom cover, a control member, a rotating member, a timing member, and a rotary cap. The timer is mechanically operated in such a way that the rotary cap is turned to a... | 06/04/2002 |
| 6344671 | Pair of FETs including a shared SOI body contact and the method of forming the FETs A method of forming a silicon on insulator (SOI) body contact at a pair of field effect transistors (FETs), a sense amplifier including a balanced pair of such FETs and a RAM including the sense amplifiers. A pair of gates are formed on a SOI silicon surf... | 02/05/2002 |
| 6297533 | LDMOS structure with via grounded source A lateral conduction MOS structure characterized by reduced source resistance and reduced pitch. The structure includes a semiconductor substrate having an epitaxial semiconductor layer thereon, the substrate and epitaxial layer being of the same conducti... | 10/02/2001 |
| 6297552 | Commonly housed diverse semiconductor die A MOSFET die and a Schottky diode die are mounted on a common lead frame pad and their drain and cathode, respectively, are connected together at the pad. The pad has a plurality of pins extending from one side thereof. The lead frame has insulated pins o... | 10/02/2001 |
| 6194776 | Semiconductor circuit device having triple-well structure in semiconductor substrate, method of fabricating the same, and mask device for fabrication of the same A semiconductor circuit device having a triple-well structure wherein a predetermined potential level is supplied to a top well without a contact region formed in the top well is disclosed. In an N-type ion implantation step for forming an N-type well reg... | 02/27/2001 |
| 6153914 | Output circuit for integrated circuits An output circuit for an integrated circuit, includes a first transistor and a second transistor connected in series between a first external voltage and a second external voltage external to the integrated circuit, respectively through first and second e... | 11/28/2000 |
| 6133632 | Commonly housed diverse semiconductor die A MOSFET die and a Schottky diode die are mounted on a common lead frame pad and their drain and cathode, respectively, are connected together at the pad. The pad has a plurality of pins extending from one side thereof. The lead frame has insulated pins o... | 10/17/2000 |
| 6100563 | Semiconductor device formed on SOI substrate In an integrated semiconductor device formed on an SOI substrate, first and second switches are switched at a predetermined cycle in a standby mode period to apply a boosted potential Vpp and a negative potential Vbb to the source of a p channel MOS trans... | 08/08/2000 |
| 6043522 | Field effect transistor array including doped two-cell isolation region for preventing latchup A semiconductor device capable of solving a problem of a conventional semiconductor device in that a high density integration cannot be expected because each cell, which includes a pair of N and P wells disposed adjacently, requires a countermeasure again... | 03/28/2000 |
| 6025621 | Integrated circuit memory devices having independently biased sub-well regions therein and methods of forming same Integrated circuit memory devices include a semiconductor substrate of first conductivity type (e.g., P-type), a first well region of second conductivity type (e.g., N-type) in the substrate and first and second nonoverlapping sub-well regions of first co... | 02/15/2000 |
| 5945712 | Semiconductor device having a SOI structure with substrate bias formed through the insulator and in contact with one of the active diffusion layers Disclosed is a semiconductor device having a silicon on insulator structure capable of achieving a high integration, and a manufacturing method of the same. The semiconductor device includes a semiconductor substrate having a silicon on insulator structur... | 08/31/1999 |
| 5942781 | Tunable threshold SOI device using back gate well A fully depleted SOI device includes a semiconductor substrate and a conductive well of a first conductivity type formed in a principal surface of the semiconductor substrate. An insulating layer is formed along the principal surface of the semiconductor ... | 08/24/1999 |
| 5861652 | Method and apparatus for protecting functions imbedded within an integrated circuit from reverse engineering The present invention provides an integrated circuit chip having one or more circuit elements that perform a desired circuit function with the circuit elements being encompassed by a molding compound that forms a package for the chip. The molding compound... | 01/19/1999 |
| 5844285 | Body contact structure for semiconductor device An improved body contact structure for a semiconductor device which is capable of forming a contact portion by using less surface area, obtaining a constant contact surface ratio between a source region and a body contact diffusion layer even when a conta... | 12/01/1998 |
| 5838047 | CMOS substrate biasing for threshold voltage control A semiconductor device includes a PMOS transistor and an NMOS transistor. In a standby state, a potential of Vcc level is applied to the substrate of the PMOS transistor and a potential of Vss level is applied to the substrate of the NMOS transistor. Ther... | 11/17/1998 |
| 5834813 | Field-effect transistor for one-time programmable nonvolatile memory element A least one one-time programmable nonvolatile (NV) memory element uses a field-effect transistor (FET) as a selectively programmed element. A short duration applied drain voltage exceeding the FET's drain-to-source breakdown voltage results in a drain sou... | 11/10/1998 |
| 5818099 | MOS high frequency switch circuit using a variable well bias An RF switch comprises a switching FET having gate and back gate terminals, an input port for receiving an RF signal, and an output port for providing substantially the RF signal during an ON state of the FET. Switching circuitry connects the back gate te... | 10/06/1998 |
| 5814884 | Commonly housed diverse semiconductor die A MOSFET die and a Schottky diode die are mounted on a common lead frame pad and their drain and cathode, respectively, are connected together at the pad. The pad has a plurality of pins extending from one side thereof. The lead frame has insulated pins o... | 09/29/1998 |
| 5814899 | SOI-type semiconductor device with variable threshold voltages In an SOI-type semiconductor device, a power supply voltage is applied to back gates of P-channel MOS transistors in a standby mode, and a voltage lower than the power supply voltage is applied to the back gates of the P-channel MOS transistors in an acti... | 09/29/1998 |
| 5808327 | AC controller An AC power controller includes at least two semiconductor regions reverse-connected in series. Each semiconductor region has an electron donor (source), an electron sink (drain) and an electron flow control electrode (gate) with characteristic curves suc... | 09/15/1998 |
| 5712509 | Semiconductor integrated circuit interconnection structures A semiconductor integrated circuit structure includes a semiconductor substrate; an electronic element disposed in the substrate; a first electrically insulating layer disposed on the substrate and the electronic element; a first electrically conducting i... | 01/27/1998 |
| 5612566 | Bidirectional blocking lateral MOSFET with improved on-resistance A bidirectional current blocking lateral power MOSFET including a source and a drain which are not shorted to a substrate, and voltages that are applied to the source and drain are both higher than the voltage at which the body is maintained (for an N-cha... | 03/18/1997 |
| 5608253 | Advanced transistor structures with optimum short channel controls for high density/high performance integrated circuits A novel MOS transistor structure for improving device scaling by improving short channel control includes a buried back gate beneath a channel region of the MOS transistor. A separate contact to a well that is electrically communicated to the buried back ... | 03/04/1997 |
| 5574298 | Substrate contact for gate array base cell and method of forming same A method for forming a gate array substrate contact and the contact resulting therefrom includes the steps of etching off polysilicon gate layers at the same time as cutting the polysilicon to form the gate array base cell (10). The method includes formin... | 11/12/1996 |
| 5554872 | Semiconductor device and method of increasing device breakdown voltage of semiconductor device In a semiconductor device including a composite substrate formed by bonding first and second semiconductor substrates to each other through an oxide film and an insulator isolation trench formed from a major surface of the first semiconductor substrate to... | 09/10/1996 |
| 5497023 | Semiconductor memory device having separately biased wells for isolation Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor m... | 03/05/1996 |
