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| Number | Title | Issue Date |
| 8183701 | Structure of stacking scatterometry based overlay marks for marks footprint reduction The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; a plurality of material layers formed on the semiconductor substrate, each of the material layers including a circuit pattern therein; and a plurality o... | 05/22/2012 |
| 8183700 | Semiconductor device having alignment mark and its manufacturing method Many holes are formed in an interlayer insulating film and the surface of the interlayer insulating film is covered with a metal film, with its surface undulated by openings or recesses formed to scatter reflection light. The size of the recesses is about the size o... | 05/22/2012 |
| 8164203 | Leadframe, semiconductor device, and method of manufacturing the same A leadframe has a die pad, first marks, and second marks, and the die pad allows thereon mounting of a first semiconductor chip. The first marks indicate a mounting region for the first semiconductor chip, the second marks indicate a mounting region for the second s... | 04/24/2012 |
| 8143731 | Integrated alignment and overlay mark An integrated alignment and overlay mark includes a pre-layer pattern for reticle-to-wafer registration implemented in an exposure tool, and a current-layer pattern incorporated with the pre-layer pattern. The pre-layer pattern and the current-layer pattern constitu... | 03/27/2012 |
| 8102064 | Electrical alignment mark set and method for aligning wafer stack An electrical alignment mark set and the method for using the same is disclosed. The electrical alignment mark set includes at least a top mark and a bottom mark. The top mark includes multiple pads disposed on a top wafer and having first pads and second pads, and ... | 01/24/2012 |
| 8097966 | Adjustable film frame aligner A film frame aligner for automatically aligning a film frame includes a film frame support, a film frame pusher for pushing the film frame, and a film frame location mechanism for locating at least one notch in the film frame. ... | 01/17/2012 |
| 8084872 | Overlay mark, method of checking local aligmnent using the same and method of controlling overlay based on the same An overlay mark is described, including N sets of parallel x-directional linear patterns respectively defined by N (≧2) exposure steps and N sets of parallel y-directional linear patterns respectively defined by the N exposure steps, and a set of parallel x-direct... | 12/27/2011 |
| 8080886 | Integrated circuit semiconductor device with overlay key and alignment key and method of fabricating the same An integrated circuit semiconductor device including a cell region formed in a first portion of a silicon substrate, the cell region including a first trench formed in the silicon substrate, a first buried insulating layer filled in the first trench, a first insulat... | 12/20/2011 |
| 8067842 | Integrated circuit package, notably for image sensor, and method of positioning The invention relates to the fabrication of integrated circuits in general, and notably the circuits of image sensors intended to form the electronic core of photographic apparatus or cameras. The chip is first aligned with respect to the package and then the packag... | 11/29/2011 |
| 8058737 | Electronic element wafer module and method for manufacturing electronic element wafer module, electronic element module and method for manufacturing electronic element module, and electronic information device An electronic element wafer module is provided, in which a transparent support substrate is disposed facing a plurality of electronic elements formed on a wafer and a plurality of wafer-shaped optical elements are disposed on the transparent support substrate, where... | 11/15/2011 |
| 8053910 | Substrate including alignment columnar member and plural protection columnar members, and method of making the same To provide a semiconductor substrate whose columnar member for alignment is difficult to fall off and a manufacturing method thereof. An alignment mark 24 (columnar member for alignment) and protection posts 26 surrounding the alignment mark 24 ... | 11/08/2011 |
| 8049345 | Overlay mark An overlay mark is used in pattern registration on a semiconductor wafer with an oxide layer. Four sets of two trenches each are formed in the oxide layer. Each trench in a set is parallel to the other trench of the same set. The trenches are configured such that ea... | 11/01/2011 |
| 8049344 | Semiconductor apparatus, manufacturing method for the semiconductor apparatus, and electronic information device A semiconductor apparatus according to the present invention includes one or a plurality of pairs of a standard pattern and an offset pattern formed therein with respect to the standard pattern as manufacturing information and other information at an information wri... | 11/01/2011 |
| 8044526 | Integrated circuit assemblies with alignment features and devices and methods related thereto A method of packaging an integrated circuit die including forming a mask window having a first aperture with a first set of alignment edges and forming an alignment feature on an uppermost surface of the integrated circuit die where the alignment feature has a secon... | 10/25/2011 |
| 8044525 | Substrate with check mark and method of inspecting position accuracy of conductive glue dispensed on the substrate The invention relates to a substrate with a check mark and a method of inspecting position accuracy of conductive glue dispensed on the substrate. The method is implemented on the substrate having at least one transfer pad and at least one check mark arranged near t... | 10/25/2011 |
| 8035238 | Driving circuit and liquid crystal display device including the same A tape carrier package (TCP) includes a film, a plurality of output leads and a plurality of input leads on the film, the plurality of output leads and the plurality of input leads being disposed on different sides, first and second TCP alignment marks arranged on o... | 10/11/2011 |
| 8022559 | Substrate for a display panel, and a display panel having the same A substrate for a display panel includes an alignment accuracy measurement mark which is used for measuring alignment accuracy between patterns on the substrate without decreasing an aperture ratio of a pixel. The substrate for a display panel includes the alignment... | 09/20/2011 |
| 8022560 | Overlay mark An overlay mark applicable in a non-volatile memory includes two first X-direction isolation structures, two first Y-direction isolation structures, two second X-direction isolation structures, two second Y-direction isolation structures, a first dielectric layer, a... | 09/20/2011 |
| 8018078 | Photo key and method of fabricating semiconductor device using the photo key A photo key has a plurality of first regions spaced apart from one another on a semiconductor substrate, and a second region surrounding the first regions, and one of the first regions and the second region constitutes a plurality of photo key regions spaced apart f... | 09/13/2011 |
| 8008788 | Semiconductor device and a method of manufacturing the same A technique for positioning a semiconductor chip and a mounting substrate with high precision using an alignment mark. In a semiconductor chip, a mark is formed in an alignment mark formation region over a semiconductor substrate in the same layer as an uppermost la... | 08/30/2011 |
| 8008789 | Substrate for a display panel, and a display panel having the same A substrate for a display panel includes an alignment accuracy measurement mark which is used for measuring alignment accuracy between patterns on the substrate without decreasing an aperture ratio of a pixel. The substrate for a display panel includes the alignment... | 08/30/2011 |
| 8004098 | Alignment key, method for fabricating the alignment key, and method for fabricating thin film transistor substrate using the alignment key An alignment key, a method for fabricating the alignment key, and a method for fabricating a thin film transistor substrate using the alignment key are provided. The alignment key includes a base substrate, a first alignment key and a first mark portion of a second ... | 08/23/2011 |
| 8004097 | Carrier wafer having alignment keys and supporting a chip Methods for manufacturing an integrated wafer scale package that reduces a potential misalignment between a chip and a pocket of a carrier substrate. According to one aspect of the present invention, a method for manufacturing a semiconductor device includes a photo... | 08/23/2011 |
| 7999399 | Overlay vernier key and method for fabricating the same An overlay vernier key includes a semiconductor substrate on which a cell region and a scribe lane region are defined, and a plurality of vernier patterns which are formed in the scribe lane region of the semiconductor substrate and arranged in a polygonal shape. Ea... | 08/16/2011 |
| 7999401 | Semiconductor device and method of manufacturing same Semiconductor device has a semiconductor chip embedded in an insulating layer. A semiconductor device comprises a semiconductor chip formed to have external connection pads and a positioning mark that is for via formation; an insulating layer containing a non-photos... | 08/16/2011 |
| 7999400 | Semiconductor device with recessed registration marks partially covered and partially uncovered A semiconductor device and a method for manufacturing such semiconductor device are provided. Specifically, in the semiconductor manufacture, a recessed alignment mark is formed on a front plane of a high distortion point glass substrate as a target for alignment fo... | 08/16/2011 |
| 7989967 | High-contrast laser mark on substrate surfaces As part of a first configured laser operation, a smooth, more reflective marking area is formed at a surface of a substrate (e.g., integral heat spreader, or IHS). In a second configured laser operation, a mark is formed at the surface of the substrate within the ma... | 08/02/2011 |
| 7989966 | Mark structure for coarse wafer alignment and method for manufacturing such a mark structure A mark structure includes on a substrate, at least four lines. The lines extend parallel to each other in a first direction and are arranged with a pitch between each pair of lines that is directed in a second direction perpendicular to the first direction. The pitc... | 08/02/2011 |
| 7989968 | Method and apparatus for measurement and control of photomask to substrate alignment A method, structure, system of aligning a substrate to a photomask. The method comprising: directing light through a clear region of the photomask in a photolithography tool, through a lens of the tool and onto a set of at least three diffraction mirror arrays on th... | 08/02/2011 |
| 7973419 | Semiconductor device and method of fabricating the same According to an aspect of the invention, there is provided a semiconductor device including a semiconductor substrate, a p-type impurity diffusion layer formed on the semiconductor substrate, and Ni silicide formed on the diffusion layer, wherein an alignment mark f... | 07/05/2011 |
| 7952213 | Overlay mark arrangement for reducing overlay shift An overlay mark arrangement for reducing the asymmetric profile and an overlay shift during an integrated circuit manufacturing process is disclosed. In one embodiment, the overlay mark arrangement may comprise a first mark, a second mark and a stress releasing mean... | 05/31/2011 |
| 7944064 | Semiconductor device having alignment post electrode and method of manufacturing the same A semiconductor device includes a semiconductor substrate which has a plurality of semiconductor device formation regions and alignment mark formation region having the same planar size as that of the semiconductor device formation region, a plurality of post electr... | 05/17/2011 |
| 7944063 | Application of 2-dimensional photonic crystals in alignment devices Alignment marks for use on substrates. In one example, the alignment marks consist of periodic 2-dimensional arrays of structures, the spacing of the structures being smaller than an alignment beam but larger than an exposure beam. ... | 05/17/2011 |
| 7928591 | Apparatus and method for predetermined component placement to a target platform The present invention relates generally to assembly techniques. According to the present invention, the alignment and probing techniques to improve the accuracy of component placement in assembly are described. More particularly, the invention includes methods and s... | 04/19/2011 |
| 7915747 | Substrate for forming semiconductor layer including alignment marks A substrate for forming a semiconductor layer includes a plurality of linear convexes or grooves on a surface of the substrate by crystal growth. The plurality of linear convexes or grooves are formed along a direction of a cleavage plane of the semiconductor layer.... | 03/29/2011 |
| 7898095 | Fiducial scheme adapted for stacked integrated circuits A method for stacking integrated circuit substrates and the substrates used therein are disclosed. In the method, an integrated circuit substrate having top and bottom surfaces is provided. The substrate is divided vertically into a plurality of layers including an ... | 03/01/2011 |
| 7893549 | Microelectronic lithographic alignment using high contrast alignment mark A microelectronic structure, and in particular a semiconductor structure, includes a substrate that includes an alignment mark comprising a substantially present element that has an atomic number at least 5 greater than a highest atomic number substantially present ... | 02/22/2011 |
| 7893550 | Semiconductor package comprising alignment members A semiconductor package comprising alignment members is provided. The semiconductor package includes a semiconductor die, first connection terminals disposed on a first surface of the semiconductor die, and a tape substrate including a substrate portion, and second ... | 02/22/2011 |
| 7875987 | Method and apparatus for measurement and control of photomask to substrate alignment A method, structure, system of aligning a substrate to a photomask. The method comprising: directing light through a clear region of the photomask in a photolithography tool, through a lens of the tool and onto a set of at least three diffraction mirror arrays on th... | 01/25/2011 |
| 7868473 | Wafer target design and method for determining centroid of wafer target A method for determining the centroid of a wafer target. In one embodiment, the method comprises a series of steps in a stepper, starting with the step of receiving a wafer, having a target set formed therein. Next, a signal is passed over the target set and over a ... | 01/11/2011 |
