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| Number | Title | Issue Date |
| 8169086 | Semiconductor chip pad structure and method for manufacturing the same A semiconductor chip pad structure and a method for manufacturing the same, wherein a flat area at the center of the terminal pad and a roughened area at the periphery thereof are provided by use of the mask photolithograph technique and the roughening process. The ... | 05/01/2012 |
| 8169087 | Semiconductor device A protective coating is formed on the surface of a semiconductor device. The surface is located on the side to which an extension portion of a wire connected to a pad of the semiconductor device is pulled. The protective coating is formed such that its height decrea... | 05/01/2012 |
| 8169085 | Semiconductor device and method of fabricating the same A semiconductor device according to one embodiment includes: a substrate; a wiring provided above the substrate and including a graphene nanoribbon layer comprising a plurality of laminated graphene nanoribbon sheets; and a wiring connecting member penetrating at le... | 05/01/2012 |
| 8138616 | Bond pad structure A bond pad structure of an integrated circuit includes a conductive pad disposed on a first dielectric layer, a first conductive block formed in a second dielectric layer below the first dielectric layer and electrically connected to the conductive pad through a fir... | 03/20/2012 |
| 8138615 | Semiconductor integrated circuit providing for wire bonding directly above an active circuit region, and manufacturing method thereof A semiconductor integrated circuit relating to one aspect of the present invention includes a power transistor, at least one or more of first metal patterns functioning as a first electrode of the power transistor and at least one or more of second metal patterns fu... | 03/20/2012 |
| 8134240 | Semiconductor device and manufacturing method for the same To provide a small, high-performance semiconductor device in which contact between adjacent wires is prevented for increased flexibility in designing a wiring layout, and an efficient method for manufacturing the semiconductor device. The semiconductor device includ... | 03/13/2012 |
| 8134239 | Address line wiring structure and printed wiring board having same An address signal line having a stub structure connects between at least three memory elements and a data transferring element and transmits address signals for the memory elements. An address terminal of the data transferring element has an impedance lower than a c... | 03/13/2012 |
| 8125092 | Semiconductor device packages and assemblies A semiconductor device package includes a carrier, one or more semiconductor devices on the carrier, and a redistribution element above the uppermost of the one or more semiconductor devices. The redistribution element includes an array of contact pads that communic... | 02/28/2012 |
| 8115323 | Semiconductor package and method of manufacturing the semiconductor package A semiconductor package and a method of manufacturing the package are provided. The semiconductor package comprises: a mounting substrate including a bond finger; at least one semiconductor chip disposed on the mounting substrate, the semiconductor chip including a ... | 02/14/2012 |
| 8115324 | Semiconductor module A semiconductor module may include a circuit substrate with a first die on the circuit substrate and a second die on the first die. The first die may include at least one first data input/output pad on a first peripheral portion of the first die and at least one fir... | 02/14/2012 |
| 8110932 | Semiconductor circuit with amplifier, bond wires and inductance compensating bond wire In one embodiment of the present invention, a semiconductor circuit including an amplifier disposed on a semiconductor substrate is disclosed. A first bond wire coupled to an input of the amplifier, a second bond wire coupled to an output of the amplifier, and a thi... | 02/07/2012 |
| 8102061 | Semiconductor device bonding wire and wire bonding method It is an object of the present invention to provide a copper-based bonding wire whose material cost is low, having excellent ball bondability, reliability in a heat cycle test or reflow test, and storage life, enabling an application to thinning of a wire used for f... | 01/24/2012 |
| 8097961 | Semiconductor device having a simplified stack and method for manufacturing thereof Embodiments of the present invention are directed to provide a semiconductor device including a semiconductor chip formed of a conductive material, a connector terminal around the semiconductor chip, which is formed of a same material for forming the semiconductor c... | 01/17/2012 |
| 8097960 | Semiconductor mounting bonding wire There is provided a bonding wire which does not cause a leaning failure or the like. A semiconductor mounting bonding wire has a breaking elongation of 7 to 20%, and stress at 1% elongation is greater than or equal to 90% of a tensile strength and is less than or eq... | 01/17/2012 |
| 8084871 | Redistribution layer enhancement to improve reliability of wafer level packaging An enhanced redistribution layer is provided that geometrically expands redistribution layer (RDL) pads associated with a ball grid array of a wafer level package (WLP) to provide tensile stress relief during temperature cycle and/or drop testing of the WLP. ... | 12/27/2011 |
| 8084870 | Semiconductor devices and electrical parts manufacturing using metal coated wires The device of this invention includes a semiconductor die attached to a bare copper lead frame and electrically coupled to a lead by a metal wire coated with a metallic material. The device would function similarly to devices where the lead frames were coated with o... | 12/27/2011 |
| 8063496 | Semiconductor integrated circuit device and method of fabricating the same A semiconductor integrated circuit device includes a semiconductor substrate including a main chip region and a pad region, a multi-layer pad structure on the pad region of the semiconductor substrate, a redistribution pad through the semiconductor substrate and in ... | 11/22/2011 |
| 8053909 | Semiconductor component having through wire interconnect with compressed bump A method for fabricating a semiconductor component with a through wire interconnect includes the step of providing a substrate having a circuit side, a back side, and a through via. The method also includes the steps of: threading a wire through the via, forming a c... | 11/08/2011 |
| 8044521 | Semiconductor device An improved reliability of a junction region between a bonding wire and an electrode pad in an operation at higher temperature is presented. A semiconductor device includes a semiconductor chip provided on a lead frame, which are encapsulated with an encapsulating r... | 10/25/2011 |
| 8044522 | Semiconductor device A semiconductor device includes a substrate; and a chip formed on the substrate and electrically connected to the substrate by a wire. The chip includes a wiring layer electrically connected to the wire; and a protective layer formed on the wiring layer. The wiring ... | 10/25/2011 |
| 8039973 | Electronic module having a multi-layer conductor for reducing its resistivity and a method of assembling such a module The module is of the type comprising an electronic component provided with a conductive face that is electrically connected to a connection member of the component by means of a conductor that is corrugated at least in part so as to define an alternating sequence of... | 10/18/2011 |
| 8039974 | Assembly of electronic components An electronic component assembly that has a supporting structure, an integrated circuit die with a plurality of contacts pads, a printed circuit board with a plurality of conductors, the integrated circuit die and the PCB being mounted to the supporting structure by... | 10/18/2011 |
| 8030781 | Bond pad structure having dummy plugs and/or patterns formed therearound A semiconductor structure is provided. In one embodiment, a bond pad is formed above one or more underlying layers of a substrate. A plurality of dummy plugs are spaced around the bond pad, the plurality of dummy plugs substantially vertically traversing the one or ... | 10/04/2011 |
| 8026615 | IC package reducing wiring layers on substrate and its carrier An IC package primarily includes a chip, a plurality of electrical connecting components, and a chip carrier including a substrate, a die-attaching layer, and at least one bonding wire. The substrate has a top surface and a bottom surface wherein the top surface inc... | 09/27/2011 |
| 8018076 | Semiconductor device, semiconductor package for use therein, and manufacturing method thereof A semiconductor package includes a substrate for mounting and fixing a semiconductor chip thereon and a connecting pattern. The substrate is provided with an elongate opening formed therein. The semiconductor chip is fixed with its surface being mounted on the subst... | 09/13/2011 |
| 8008784 | Package including a lead frame, a chip and a sealant A package and a fabricating method thereof are provided. The package includes a lead frame, a chip and a sealant. The lead frame has a notch and a plurality of first notch-side leads, a plurality of first notch-side pads, a plurality of second notch-side leads and a... | 08/30/2011 |
| 8008785 | Microelectronic assembly with joined bond elements having lowered inductance A microelectronic assembly includes a semiconductor chip having chip contacts exposed at a first face and a substrate juxtaposed with a face of the chip. A conductive bond element can electrically connect a first chip contact with a first substrate contact of the su... | 08/30/2011 |
| 8004094 | Copper alloy bonding wire for semiconductor device The present invention provides a semiconductor-device copper-alloy bonding wire which has an inexpensive material cost, ensures a superior ball joining shape, wire joining characteristic, and the like, and a good loop formation characteristic, and a superior mass pr... | 08/23/2011 |
| 7989961 | Redistribution layer enhancement to improve reliability of wafer level packaging An enhanced redistribution layer is provided that geometrically expands redistribution layer (RDL) pads associated with a ball grid array of a wafer level package (WLP) to provide tensile stress relief during temperature cycle and/or drop testing of the WLP. ... | 08/02/2011 |
| 7989962 | Bonding pad for preventing pad peeling A bonding pad includes multiple metal layers, insulation layers disposed between the multiple metal layers, and a fixing pin coupled between the uppermost metal layer and an underlying metal layer of the multiple metal layers, where a bonding is performed on the upp... | 08/02/2011 |
| 7986047 | Wire bond interconnection A wire bond interconnection between a die pad and a bond finger includes a support pedestal at a bond site of the lead finger, a ball bond on the die pad, and a stitch bond on the support pedestal, in which a width of the lead finger at the bond site is less than a ... | 07/26/2011 |
| 7969021 | Bonding wire for semiconductor device and method for producing the same A bonding wire for a semiconductor device has a core wire and a periphery comprising a conductive metal mainly composed of an element common to both and/or an alloy or alloys of said metal and, between the core wire and the periphery, a diffusion layer or an interme... | 06/28/2011 |
| 7969025 | Electric power semiconductor device An electric power semiconductor device including first and second circuit patterns formed on main surfaces of first and second insulating substrates, respectively, first and second semiconductor chips mounted on the first and second circuit patterns, respectively, a... | 06/28/2011 |
| 7969022 | Die-to-die wire-bonding Methods for die-to-die wire-bonding, and devices and systems formed thereby, are described herein. A die to die wire-bonding method may comprise bonding a first conductive bump having a first bump size to a first die pad; bonding a first wire to a second die pad, th... | 06/28/2011 |
| 7969023 | Integrated circuit package system with triple film spacer having embedded fillers and method of manufacture thereof An integrated circuit package in package system includes: providing a substrate with a first wire-bonded die mounted thereover, and connected to the substrate with bond wires; mounting a triple film spacer above the first wire-bonded die, the triple film spacer havi... | 06/28/2011 |
| 7969024 | Semiconductor package with joint reliability, entangled wires including insulating material A semiconductor package with improved joint reliability and a method of fabricating the semiconductor package are disclosed. A conductive connector may be formed on a surface of a semiconductor wafer on which semiconductor devices may be arranged. A first insulating... | 06/28/2011 |
| 7960845 | Flexible contactless wire bonding structure and methodology for semiconductor device A semiconductor device such as a field-effect transistor, improved to reduce device resistance, comprises a leadframe which includes a die paddle integral with a first set of leads and a second set of leads that is electrically isolated from the first set, a semicon... | 06/14/2011 |
| 7960846 | Semiconductor device having improved solder joint and internal lead lifetimes A semiconductor chip is mounted on a flexible wiring board through the interposition of an elastomer. The flexible wiring board is made up of a tape on which wiring is fixed. A part of the wiring is projected beyond the edge of the tape, extended in the direction of... | 06/14/2011 |
| 7952211 | Semiconductor assembly with component pads attached on die back side One or more electronic components can be mounted on the back side of a semiconductor die. The components can be passive components, active components, or combinations thereof. The components can be soldered to signal routes on the back side of the die, the signal ro... | 05/31/2011 |
| 7948093 | Memory IC package assembly having stair step metal layer and apertures Disclosed is a low cost memory IC package assembly having a first metal layer bonded to the die and a dielectric insulating layer with circuits and with apertures to expose the first metal layer bonded thereto. ... | 05/24/2011 |
