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| Number | Title | Issue Date |
| 8188606 | Solder bump interconnect A semiconductor package includes a device pad on a substrate. A polybenzoxazole (PBO) layer overlies the substrate, and the PBO layer has an opening to expose the device pad. A redistribution layer (RDL) comprises a landing pad, and the RDL is positioned on the PBO ... | 05/29/2012 |
| 8183698 | Bond pad support structure for semiconductor device According to certain embodiments, integrated circuits are fabricated using brittle low-k dielectric material to reduce undesired capacitances between conductive structures. To avoid permanent damage to such dielectric material, bond pads are fabricated with support ... | 05/22/2012 |
| 8125091 | Wire bonding over active circuits A semiconductor device includes a semiconductor die mounted over a package substrate. The die has a bond pad located thereover. A stud bump consisting substantially of a first metal is located on the bond pad. A wire consisting substantially of a different second me... | 02/28/2012 |
| 8115320 | Bond pad structure located over active circuit structure A bond pad structure located over an active circuit structure is disclosed. The bond pad structure includes a bond pad, a passivation layer and a topmost metal layer in the active circuit structure. The passivation layer covers the bond pad and has an opening, and t... | 02/14/2012 |
| 8110931 | Wafer and semiconductor package A wafer defines a plurality of chips arranged in array manner. Each chip includes at least one aluminum pad and a middle material. The middle material covers the aluminum pad and is mounted on the aluminum pad. ... | 02/07/2012 |
| 8080884 | Mounting structure and mounting method A mounting structure of the present invention includes a semiconductor element 101, a circuit board 301 having electrodes 302 opposed to electrodes 102 of the semiconductor element 101, and conductive two-layer bumps 213. Se... | 12/20/2011 |
| 8076785 | Semiconductor device A semiconductor device includes a semiconductor element having a main surface where an outside connection terminal pad is provided. The semiconductor element is connected to a conductive layer on a supporting board via a plurality of convex-shaped outside connection... | 12/13/2011 |
| 8053906 | Semiconductor package and method for processing and bonding a wire A copper bonding wire includes a line portion and a non-spherical block portion. The non-spherical block portion is physically connected to the line portion, and the cross-sectional area of the non-spherical block portion is bigger than that of the line portion.... | 11/08/2011 |
| 8018075 | Semiconductor package, method for enhancing the bond of a bonding wire, and method for manufacturing a semiconductor package A wire bonding structure of a semiconductor package includes a bonding wire, a pad and a non-conductive adhesive material. The bonding wire includes a line portion and a block portion, wherein the block portion is physically connected to the line portion, and the se... | 09/13/2011 |
| 7977803 | Chip structure with bumps and testing pads A chip structure comprising a silicon substrate, a MOS device, dielectric layers, a metallization structure, a passivation layer, a plurality of metal layers and a polymer layer. The metallization structure comprises a first circuit layer and a second circuit layer ... | 07/12/2011 |
| 7973418 | Solder bump interconnect for improved mechanical and thermo-mechanical performance An apparatus and method for a semiconductor package including a bump on input-output (IO) structure are disclosed involving a device pad, an under bump metal pad (UBM), a polymer, and a passivation layer. The shortest distance from the center of the device pad to it... | 07/05/2011 |
| 7952209 | Integrated circuit package system with pad to pad bonding An integrated circuit package system includes an integrated circuit die, a first controlled bump over the integrated circuit die, a second controlled bump over the integrated circuit die, and a connector between the first controlled bump and the second controlled bu... | 05/31/2011 |
| 7944058 | Semiconductor device and process for fabricating the same A thin stacked semiconductor device has a plurality of circuits that are laminated and formed sequentially in a specified pattern to form a multilayer wiring part. At the stage for forming the multilayer wiring part, a filling electrode is formed on the semiconducto... | 05/17/2011 |
| 7915741 | Solder bump UBM structure Disclosed is an under bump metallization structure including a plurality of metal or metal alloy layers formed on chip bond pads. The disclosed UBM structure has a stress improvement on the semiconductor device because the thickness of the copper-base layer is reduc... | 03/29/2011 |
| 7888807 | Method of producing wire-connection structure, and wire-connection structure For electrically connecting a wiring formed on one surface of an insulating substrate such as an FPC to an individual electrode arranged facing the other surface of the substrate, firstly, a through hole and a notch are formed by irradiating a laser beam from above ... | 02/15/2011 |
| 7884487 | Rotation joint and semiconductor device having the same Provided are a rotation joint capable of compensating for a mismatch due to thermal expansion and a semiconductor device having the same. The rotation joint can include a support member and a first contact member coupled to a first portion of the support member such... | 02/08/2011 |
| 7880315 | Methods for bonding and micro-electronic devices produced according to such methods One inventive aspect is related to a method of bonding two elements and micro-electronic devices produced according to such methods. In one aspect, a micro-electronic device includes a first and a second element, bonded together by a joining structure. The joining s... | 02/01/2011 |
| 7855461 | Chip structure with bumps and testing pads A chip structure comprising a semiconductor substrate, a plurality of dielectric layers, a plurality of circuit layers, a passivation layer, a metal layer and at least a bump. The semiconductor substrate has a plurality of electronic devices positioned on a surface ... | 12/21/2010 |
| 7808114 | Circuit device and method of manufacturing thereof A circuit device of preferred embodiments of the present invention includes: a circuit element with electrodes formed in a peripheral part thereof; connecting portions connected to surfaces of the electrodes; and redistribution lines which are continuous to the resp... | 10/05/2010 |
| 7791210 | Semiconductor package having discrete non-active electrical components incorporated into the package Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate having an integrated circuit die attached thereto. The substrate further includes at least one signal layer having a plurality of electrical signal traces forme... | 09/07/2010 |
| 7786600 | Circuit substrate having circuit wire formed of conductive polarization particles, method of manufacturing the circuit substrate and semiconductor package having the circuit wire A circuit substrate includes a substrate body having a first terminal and a second terminal separated from the first terminal. A circuit wire includes a wiring unit for electrically connecting the first and second terminals by electrically connecting conductive pola... | 08/31/2010 |
| 7728442 | Semiconductor device and a method of manufacturing the same A semiconductor device manufacturing technique which allows reduction of semiconductor chip size. First, a pad and other wires are formed over an insulating film. A surface protective film is formed over the insulating film including the pad and wires, and an openin... | 06/01/2010 |
| 7719120 | Multi-component integrated circuit contacts An integrated circuit connection is describe that includes a first, securing member and a second, connection member. The first member, in an embodiment, is a spike that has a portion of its body fixed in a layer of an integrated circuit structure and extends outward... | 05/18/2010 |
| 7692314 | Wafer level chip scale package and method for manufacturing the same Provided is a wafer level chip scale package that reduces the parasitic capacitance generated between ball pads and the solder balls, and enhances the joint reliability between the ball pads and the solder balls. The wafer level chip scale package provides a conduct... | 04/06/2010 |
| 7663250 | Wafer level package and manufacturing method thereof A wafer level package and a manufacturing method thereof capable of reducing stress between an under bump metal and a bump. The wafer level package includes a substrate provided with a plurality of chip pads on a top surface; a first passivation layer to expose the ... | 02/16/2010 |
| 7589426 | Semiconductor assemblies including redistribution layers and packages and assemblies formed therefrom Methods for creating redistribution layers for only selected dice, such as known good dice, to form relatively thin semiconductor component assemblies and packages, and the assemblies and packages created by the methods, are disclosed. A sacrificial layer is deposit... | 09/15/2009 |
| 7586200 | Light emitting diode chip with reflective layer thereon A light emitting diode including a substrate, a semiconductor layer, multiple electrodes, a passivation layer, multiple under bump metallurgy (UBM) layers and a reflective layer is provided. The semiconductor layer is disposed on the substrate. The electrodes and th... | 09/08/2009 |
| 7573140 | Semiconductor device and method for manufacturing the same A semiconductor device includes: a semiconductor substrate that has an integrated circuit; a plurality of electrodes that is formed on the semiconductor substrate, the plurality of the electrodes being electrically coupled to the integrated circuit; a passivation fi... | 08/11/2009 |
| 7554206 | Microelectronic packages and methods therefor A microelectronic assembly includes a microelectronic package having a microelectronic element with faces and contacts, a flexible substrate spaced from and overlying a first face of the microelectronic element, and a plurality of conductive posts extending from the... | 06/30/2009 |
| 7511381 | Thin film transistor and method of manufacturing the same A thin film transistor (TFT) and a method of manufacturing the same are provided. The TFT includes a transparent substrate, an insulating layer on a region of the transparent substrate, a monocrystalline silicon layer, which includes source, drain, and channel regio... | 03/31/2009 |
| 7485971 | Electronic device package An electronic device package is described that includes a non-metal die attached adhesive. The die attach is positioned in discrete positions on a surface to which the die will be fixed. The die is placed on the discrete die attach. The die attach, in an embodiment,... | 02/03/2009 |
| 7479704 | Substrate improving immobilization of ball pads for BGA packages A substrate improving immobilization of ball pads for BGA packages mainly comprises a substrate core, a plurality of ball pads and a solder resist layer. Each of the ball pads has a metal pad and at least a metal nail. The metal pads are adhered on a surface of the ... | 01/20/2009 |
| 7470996 | Packaging method A packaging method includes ultrasonically bonding a semiconductor device and a substrate together via bumps that include gold as a main component thereof. A contact surface of a primary bump on a surface of an aluminum pad on one side of the substrate contacts and ... | 12/30/2008 |
| 7468559 | Semiconductor integrated circuit package having electrically disconnected solder balls for mounting Integrated circuit packages that connect solder balls between solder ball pads of a die and substrate pads of a printed circuit board (PCB). The solder balls are electrically disconnected from any circuit of the die, i.e., “dummy” solder balls, and are used to t... | 12/23/2008 |
| 7443041 | Packaging of a microchip device A method of packaging a microchip device, an interposer for packaging, and a packaged microchip device. An interposer is placed on microchip devices. The interposer includes an aperture which extends from the interposer surface where external electrical contacts are... | 10/28/2008 |
| 7443036 | Manufacturing method of semiconductor device The manufacturing method of the semiconductor device of the present invention has a step forming solder balls on the circuit face of a mother chip, a step making flip chip bonding of the daughter chip after the step forming solder balls on the circuit face of the mo... | 10/28/2008 |
| 7443040 | Aluminum cap with electroless nickel/immersion gold A resulting solder bump structure comprising the following steps. A structure having a metal bond pad formed thereover is provided. A patterned cover layer is formed over the structure. The patterned cover layer including an opening exposing a portion of the metal b... | 10/28/2008 |
| 7436073 | Junction structure for a terminal pad and solder, and semiconductor device having the same A junction structure, and a semiconductor device including the same, for a junction of a terminal pad and solder, including an underlying base on which said terminal pad is formed; a nickel layer disposed on the terminal pad; a palladium layer or a gold layer dispos... | 10/14/2008 |
| 7436063 | Packaging substrate and semiconductor device A packaging substrate according to the present invention is a packaging substrate to which a semiconductor chip having a plurality of connection metal bodies on a surface thereof is bonded with the surface opposed to the packaging substrate and comprises a wiring pr... | 10/14/2008 |
| 7435619 | Method of fabricating a 3-D package stacking system The present invention provides a system for 3D package stacking system, comprising providing a substrate, attaching a ball grid array package, in an inverted position, to the substrate, forming a lower package, the lower package having the ball grid array package an... | 10/14/2008 |
