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| Number | Title | Issue Date |
| 8188605 | Components joining method and components joining structure To provide a components joining method and a components joining structure which can realize joining of components while securing conduction at a low electrical resistance with high reliability. In a construction in which by using a solder paste containing sol... | 05/29/2012 |
| 8183697 | Apparatus and methods of forming an interconnect between a workpiece and substrate Embodiments of an apparatus and methods of forming interconnect between a workpiece and substrate and its application to packaging of microelectronic devices are described herein. Other embodiments may be described and claimed. ... | 05/22/2012 |
| 8138612 | Semiconductor device A semiconductor device including: a semiconductor substrate including an electrode; a resin protrusion formed on the semiconductor substrate and including a plurality of first portions and a second portion disposed between two of the first portions adjacent to each ... | 03/20/2012 |
| 8125090 | Semiconductor power module Use of Pb-free solder has become essential due to the environmental problem. A power module is formed by soldering substrates with large areas. It is known that in Sn-3Ag-0.5Cu which hardly creeps and deforms with respect to large deformation followed by warpage of ... | 02/28/2012 |
| 8093728 | Connection by fitting together two soldered inserts A connection device between two components includes a hollow conductive insert, into which is fitted another conductive insert, the electrical connection between the two inserts being provided by means of a solder element. ... | 01/10/2012 |
| 8039971 | Electronic circuit arrangement Electronic circuit arrangement, includes a chip and a chip carrier having a substrate and a chip contact location. At least the chip contact location is provided with a soldering layer. The chip includes a bonding layer. A silver layer for eutectic bonding with the ... | 10/18/2011 |
| 8018074 | Components joining method and components joining structure To provide a components joining method and a components joining structure which can realize joining of components while securing conduction at a low electrical resistance with high reliability. In a construction in which by using a solder paste containing sol... | 09/13/2011 |
| 7999395 | Pillar structure on bump pad Substrates including conductive pads for coupling the substrates to a microelectronic device and/or package are described herein. Embodiments of the present invention provide substrates comprising one or more conductive pads including a base portion and a pillar por... | 08/16/2011 |
| 7999394 | Void reduction in indium thermal interface material Thermal interface materials and method of using the same in packaging are provided. In one aspect, a thermal interface material is provided that includes an indium preform that has a first surface and a second surface opposite to the first surface, an interior porti... | 08/16/2011 |
| 7982320 | Arrangement for solder bump formation on wafers An apparatus and a process for the manufacture of a solder-bump adhered wafer substrate for use in the semiconductor industry, comprising one or more of the following steps including: arranging a first compressive member and a second compressive member in an opposed... | 07/19/2011 |
| 7973417 | Integrated circuit and method of fabricating the same An article including a substrate having a blind hole formed therein, wherein the blind hole is defined by a floor and a sidewall and a solder connection is provided. The solder connection may couple a first contact pad to a second contact pad. The first contact pad ... | 07/05/2011 |
| 7956472 | Packaging substrate having electrical connection structure and method for fabricating the same A packaging substrate having an electrical connection structure and a method for fabricating the same are provided. The packaging substrate have a substrate body with a plurality of conductive pads on a surface thereof; a solder mask layer disposed on the substrate ... | 06/07/2011 |
| 7932613 | Interconnect structure for a semiconductor device A semiconductor device having a device substrate is provided. The semiconductor device includes an electrically-conductive pad formed overlying the device substrate, and an electrically-conductive platform formed overlying the electrically-conductive pad and enclosi... | 04/26/2011 |
| 7928585 | Sprocket opening alignment process and apparatus for multilayer solder decal A process for aligning at least two layers in an abutting relationship with each other comprises forming a plurality of sprocket openings in each of the layers for receiving a sprocket of diminishing diameters as the sprocket extends outwardly from a base, with the ... | 04/19/2011 |
| 7902680 | Layered structure, electron device, and an electron device array having a variable wettability layer and semiconductor layer formed thereon A layered structure comprises a variable wettability layer including a material that changes a critical surface tension in response to energy provided thereto, the wettability changing layer including at least a high surface energy part of large critical surface ten... | 03/08/2011 |
| 7851928 | Semiconductor device having substrate with differentially plated copper and selective solder A semiconductor device having an insulating substrate with differentially plated metal and selective solder. Chip 221 with contact studs 223 is attached onto the traces 203 on tape 101. The traces, which are unprotected by soldermask 1... | 12/14/2010 |
| 7843074 | Underfill for light emitting device A light emitting chip is disposed on a support surface. A plurality of bonding bumps are disposed in a gap between the light emitting chip and the support surface. The plurality of bonding bumps provide at least one electrical power input path to the light emitting ... | 11/30/2010 |
| 7843075 | Apparatus and methods of forming an interconnect between a workpiece and substrate Embodiments of an apparatus and methods of forming interconnect between a workpiece and substrate and its application to packaging of microelectronic devices are described herein. Other embodiments may be described and claimed. ... | 11/30/2010 |
| 7838999 | System and method of manufacture for interconnecting an integrated circuit and a substrate An integrated circuit/substrate interconnect apparatus and method of manufacture are provided. Included is a substrate with a plurality of wells and a landing pad formed in each of the wells. The substrate further includes a seed layer deposited in each of the wells... | 11/23/2010 |
| 7830022 | Semiconductor package A semiconductor package is disclosed. One embodiment provides a semiconductor package singulated from a wafer includes a chip defining an active surface, a back side opposite the active surface, and peripheral sides extending between the active surface and the back ... | 11/09/2010 |
| 7804179 | Plastic ball grid array ruggedization A method and product which provides a thin metal or ceramic plate to the top of a plastic grid array (PGA) as a stiffener to maintain its flatness over temperature during a column attach process, and the columns are used for attachment to circuit boards or other cir... | 09/28/2010 |
| 7786599 | Semiconductor device with an improved solder joint A semiconductor device with an improved solder joint system is described. The solder system includes two copper contact pads connected by a body of solder and the solder is an alloy including tin, silver, and at least one metal from the transition groups IIIA, IVA, ... | 08/31/2010 |
| 7772707 | Methods for wafer-level packaging of microelectronic devices and microelectronic devices formed by such methods Methods for packaging microelectronic devices, microelectronic workpieces having packaged dies, and microelectronic devices are disclosed herein. One aspect of the invention is directed toward a microelectronic workpiece comprising a substrate having a device side a... | 08/10/2010 |
| 7732932 | Semiconductor chips with crack stop regions for reducing crack propagation from chip edges/corners Structures and a method for forming the same. The structure includes a semiconductor substrate, a transistor on the semiconductor substrate, and N interconnect layers on top of the semiconductor substrate, N being a positive integer. The transistor is electrically c... | 06/08/2010 |
| 7732933 | Semiconductor chip and TAB package having the same A semiconductor chip, having an active surface including a peripheral area and a central area, presents a connection area formed on a portion of the peripheral area. The semiconductor chip includes output pads formed in the peripheral area of the active surface and ... | 06/08/2010 |
| 7728441 | Method for mounting a semiconductor package onto PCB A method for mounting a semiconductor package onto PCB is disclosed. A semiconductor package is provided, which comprises a plurality of outer terminals exposed out of an encapsulant. A PCB is provided and has a surface with a plurality of contact pads. Each contact... | 06/01/2010 |
| 7723854 | Assembly and method of assembling by soldering an object and a support This assembly of an object and a support is achieved by using solder bumps. At least two wettability areas are made respectively on an object and on a support. Each solder bump ensures electrical contact and mechanical fixing firstly to one of the wettability areas ... | 05/25/2010 |
| 7719119 | Semiconductor device, electronic apparatus comprising the same, and method for fabrication of substrate for semiconductor device used therein A semiconductor device has upper electrodes and external terminals which are protruding above the both surfaces of a substrate for semiconductor device and connected to each other by penetrating electrodes, a first insulating film covering at least a metal pattern e... | 05/18/2010 |
| 7705471 | Conductive bump structure of circuit board and method for forming the same A conductive bump structure of a circuit board and a method for forming the same are proposed. A conductive layer is formed on an insulating layer on the surface of the circuit board. A first resist layer is formed on the conductive layer and a plurality of first op... | 04/27/2010 |
| 7701069 | Solder interface locking using unidirectional growth of an intermetallic compound A ball grid array device includes a substrate, further including a first major surface and a second major surface. An array of pads is positioned on one of the first major surface or the second major surface. At least some of the pads include a barrier layer having ... | 04/20/2010 |
| 7692313 | Substrate and semiconductor package for lessening warpage A substrate with reduced substrate warpage and a semiconductor package utilizing the substrate are revealed. The substrate primarily comprises a core where a wiring layer and a first solder mask are formed on one surface of the core, and a second solder mask and a d... | 04/06/2010 |
| 7683493 | Intermetallic diffusion block device and method of manufacture One embodiment of the present invention is directed to an under bump metallurgy material. The under bump metallurgy material of this embodiment includes an adhesion layer and a conduction layer formed on top of the adhesion layer. The under bump metallurgy material ... | 03/23/2010 |
| 7667335 | Semiconductor package with passivation island for reducing stress on solder bumps A flip chip style semiconductor package has a substrate with a plurality of active devices formed thereon. A contact pad is formed on the substrate. An under bump metallization (UBM) layer is in electrical contact with the contact pad. A passivation layer is formed ... | 02/23/2010 |
| 7626275 | Semiconductor device A semiconductor device includes a semiconductor substrate, a first metal film on a back surface of the semiconductor substrate, a second metal film on the first metal film, and a third metal film on the second metal film. The first metal film forms an alloy with a s... | 12/01/2009 |
| 7626276 | Method and apparatus for providing structural support for interconnect pad while allowing signal conductance A method provides an interconnect structure having enhanced structural support when underlying functional metal layers are insulated with a low modulus dielectric. A first metal layer having a plurality of openings overlies the substrate. A first electrically insula... | 12/01/2009 |
| 7626274 | Semiconductor device with an improved solder joint A semiconductor device with an improved solder joint system is described. The solder system includes two copper contact pads connected by a body of solder and the solder is an alloy including tin, silver, and at least one metal from the transition groups IIIA, IVA, ... | 12/01/2009 |
| 7612455 | Layered structure for electron device including regions of different wettability, electron device and electron device array that uses such a layered structure A layered structure comprises a variable wettability layer including a material that changes a critical surface tension in response to energy provided thereto, the wettability changing layer including at least a high surface energy part of large critical surface ten... | 11/03/2009 |
| 7608929 | Electrical connector structure of circuit board and method for fabricating the same An electrical connector structure of circuit board and a method for fabricating the same are proposed. A circuit board having a conductive layer is formed with a first resist layer and a second resist layer thereon, so as to form electrical connection pads and metal... | 10/27/2009 |
| 7608930 | Semiconductor device and method of manufacturing semiconductor device This semiconductor device includes a semiconductor chip, and a lead arranged around the semiconductor chip to extend in a direction intersecting with the side surface of the semiconductor chip, and having at least an end farther from the semiconductor chip bonded to... | 10/27/2009 |
| 7605481 | Nickel alloy sputtering target and nickel alloy thin film The present invention relates to a nickel alloy sputtering target comprising 1 to 30 at % of Cu; 2 to 25 at % of at least one element selected from among V, Cr, Al, Si, Ti and Mo; remnant Ni and unavoidable impurities so as to inhibit the Sn diffusion between a sold... | 10/20/2009 |
