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| Number | Title | Issue Date |
| 8164197 | Semiconductor device having multilayer interconnection structure A semiconductor device according to the present invention includes: a first interlayer dielectric film; a lower wire formed on the first interlayer dielectric film; a second interlayer dielectric film formed on the first interlayer dielectric film and the lower wire... | 04/24/2012 |
| 8129845 | Semiconductor device and method of forming interconnect structure in non-active area of wafer A semiconductor wafer includes a plurality of semiconductor die. Contact pads are formed on an active area of the semiconductor die and non-active area of the semiconductor wafer between the semiconductor die. Solder bumps are formed on the contact pads in both the ... | 03/06/2012 |
| 8072081 | Microelectromechanical system package A microelectromechanical system package includes a chip carrier, a first microelectromechanical system chip, a silicon cover, a layer of metal, a plurality of first bonding wires and a sealant. The first microelectromechanical system chip is positioned on the chip c... | 12/06/2011 |
| 8072080 | Connection structure, electro-optical device, and method for production of electro-optical device The invention provides a connection structure including: a first electro-conductive film that is formed on a substrate; an insulation film that is formed on the first electro-conductive film, an end surface of the insulation film facing in a direction in which an en... | 12/06/2011 |
| 8053902 | Isolation structure for protecting dielectric layers from degradation An integrated circuit structure includes a semiconductor substrate; and an interconnect structure overlying the semiconductor substrate. A solid metal ring is formed in the interconnect structure, with substantially no active circuit being inside the solid metal rin... | 11/08/2011 |
| 8049339 | Semiconductor package having isolated inner lead A semiconductor package with isolated inner lead(s) is revealed. A chip is disposed on a leadframe segment and encapsulated by an encapsulant. The leadframe segment includes a plurality of leads, an isolated lead, and an external lead where each lead has an internal... | 11/01/2011 |
| 8026611 | Stacked microelectronic packages having at least two stacked microelectronic elements adjacent one another A microelectronic assembly including a first and second microelectronic elements. Each of the microelectronic elements have oppositely-facing first and second surfaces and edges bounding the surfaces. The first microelectronic element is disposed on the second micro... | 09/27/2011 |
| 7969014 | Power layout of integrated circuits and designing method thereof The invention discloses a technique for designing the power layout of an integrated circuit. The power layout design forms a power mesh and a power ring with a plurality of metal trunks with uniform line width. In particular, the power ring includes a plurality of m... | 06/28/2011 |
| 7939946 | Chip with a vertical contact structure A chip with a chip plane includes a functional area, a contact structure vertical with respect to the chip plane for connecting the functional area, which includes a conductive material, which has a predetermined length, and a vertical dummy-contact structure, which... | 05/10/2011 |
| 7932610 | Semiconductor integrated circuit having improved power supply wiring In a semiconductor integrated circuit including a plurality of cells, a supplementary power-supply wire is disposed between a lattice-shaped upper power-supply wire and a lower cell power-supply wire for cases in which power is supplied from the upper power-supply w... | 04/26/2011 |
| 7911063 | Semiconductor device In a semiconductor device according to an aspect of the invention, a direction in which a fourth metal interconnection layer located on a semiconductor layer is extended is orthogonal to a direction in which third interconnection layers ML30 and ML37 l... | 03/22/2011 |
| 7902673 | Semiconductor device A tooling method for fabricating semiconductor devices includes identifying two adjacent device lines having a device-to-device spacing width in an active region of a substrate, performing an operation to selectively define a first region as a region between the two... | 03/08/2011 |
| 7898089 | Semiconductor workpiece The present invention provides an apparatus and method for use in processing semiconductor workpieces. The new apparatus and method allows for the production of thinner workpieces that at the same time remain strong. Particularly, a chuck is provided that includes a... | 03/01/2011 |
| 7898088 | I/O pad structures for integrated circuit devices A semiconductor device, including methods and arrangements for making the same, are described. The device includes an integrated circuit die having a plurality of bond pads. At least one bond pad on the active surface of the die is an extended I/O pad. Each extended... | 03/01/2011 |
| 7872355 | Semiconductor integrated circuit and method of designing semiconductor integrated circuit A semiconductor integrated circuit has: a power pad placed on a chip; and a circuit group connected to the power pad through a power wiring structure. The power wiring structure includes: a plurality of first power wirings and a plurality of second power wirings tha... | 01/18/2011 |
| 7868461 | Embedded interconnects, and methods for forming same The present invention relates to a semiconductor device comprising first and second active device regions that are located in a semiconductor substrate and are isolated from each other by an isolation region therebetween, while the semiconductor device comprises a f... | 01/11/2011 |
| 7859116 | Exposed metal bezel for use in sensor devices and method therefor A sensor package has a substrate. A sensor die having an inactive surface is bonded to the substrate. An active surface of the sensor die is exposed. A portion of the active surface of the sensor die has an active imaging area. A metal bezel is formed on the active ... | 12/28/2010 |
| 7851926 | Semiconductor device A semiconductor device includes first underlying lines in an underlying wiring layer electrically connected to and shaped like a first semiconductor region, second underlying lines in the underlying wiring layer electrically connected to and shaped like a second sem... | 12/14/2010 |
| 7847410 | Interconnect of group III-V semiconductor device and fabrication method for making the same An interconnect of the group III-V semiconductor device and the fabrication method for making the same are described. The interconnect includes a first adhesion layer, a diffusion barrier layer for preventing the copper from diffusing, a second adhesion layer and a ... | 12/07/2010 |
| 7816792 | Semiconductor device with conductive interconnect One or more embodiments are related to a semiconductor structure, comprising: a semiconductor chip; a conductive layer comprising at least a first conductive pathway and a second conductive pathway spacedly disposed from the first conductive pathway, the first condu... | 10/19/2010 |
| 7812456 | Semiconductor device and a method of manufacturing the same A semiconductor device having redistribution interconnects in the WPP technology and improved reliability, wherein the redistribution interconnects have first patterns and second patterns which are electrically separated from each other within the plane of the semic... | 10/12/2010 |
| 7800236 | Semiconductor die and method for forming a semiconductor die having power and ground strips that are oriented diagonally A method for forming a semiconductor die and a flip-chip integrated circuit device are disclosed that include a power and ground mesh that is oriented diagonally. A layout of a semiconductor die is formed by generating a first integrated circuit design and copying a... | 09/21/2010 |
| 7791208 | Power semiconductor arrangement A power semiconductor arrangement is provided that includes a power semiconductor chip being electrically connected to a set of plug-like elements with at least two plug-like elements and further including a sheet metal strip line including a set of openings receivi... | 09/07/2010 |
| 7732928 | Structure for protecting electronic packaging contacts from stress A structure for protecting electronic package contacts is provided. The structure includes at least an electronic contact mounted on a chip, a dielectric layer, a conductor trace line and a protective layer. The protective layer is used to prevent stresses from bein... | 06/08/2010 |
| 7709967 | Shapes-based migration of aluminum designs to copper damascene An interconnect structure, method of fabricating the interconnect structure and method of designing the interconnect structure for use in semiconductor devices. The interconnect structure includes a damascene metal wire having a pattern of dielectric filled holes. | 05/04/2010 |
| 7701065 | Device including a semiconductor chip having a plurality of electrodes A device, including a semiconductor chip having a plurality of first electrodes is disclosed. A plurality of second electrodes is arranged on a first surface of the semiconductor chip. A first electrically conductive layer is applied over a first section of the firs... | 04/20/2010 |
| 7692309 | Configuring structured ASIC fabric using two non-adjacent via layers An application-specific integrated circuit (ASIC) is customized using two non-adjacent via layers. An array of logic cells, each including a plurality of logic devices, are arranged in a plurality of non-customized base layers. A first routing grid, which includes a... | 04/06/2010 |
| 7629694 | Interconnections for crosswire arrays A system includes a first crosswire array, having first input wiring and first output wiring, and a second crosswire array, having second input wiring and second output wiring, wherein the first crosswire array and second crosswire array are provided on or above the... | 12/08/2009 |
| 7626272 | Via configurable architecture for customization of analog circuitry in a semiconductor device A semiconductor device having a plurality of layers and a plurality of circuit elements arranged in tiles. At least one of the plurality of layers in the semiconductor device may be a via layer configured to determine the connections of the plurality of circuit elem... | 12/01/2009 |
| 7602069 | Micro electronic component with electrically accessible metallic clusters A micro electronic component, preferably in the form of an electronic memory, includes the use of clusters as an electronic memory. Also disclosed as part of the present invention is a method for fabricating a micro electronic component. The present invention contem... | 10/13/2009 |
| 7557451 | Electro-optical device and electronic apparatus An electro-optical device includes a substrate that holds an electro-optical material; and a flexible substrate that is connected to the substrate. The flexible substrate has a first connecting portion that is arranged on one surface of the substrate; and a second c... | 07/07/2009 |
| 7554202 | Semiconductor integrated circuit device Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are dis... | 06/30/2009 |
| 7550854 | Integrated interconnect arrangement An explanation is given of an integrated interconnect arrangement having a plurality of interconnects that cross over one another at two crossover sections. By virtue of this measure, it is possible to achieve a uniform current flow in all three interconnects even a... | 06/23/2009 |
| 7550855 | Vertically spaced plural microsprings A plurality of vertically spaced-apart microsprings are provided to increase microspring contact force, contact area, contact reliability, and contact yield. The microspring material is deposited, either as a single layer or as a composite of multiple sub layers, to... | 06/23/2009 |
| 7514795 | Semiconductor integrated circuit having improved power supply wiring In a semiconductor integrated circuit including a plurality of cells, a supplementary power-supply wire is disposed between a lattice-shaped upper power-supply wire and a lower cell power-supply wire for cases in which power is supplied from the upper power-supply w... | 04/07/2009 |
| 7474002 | Semiconductor device having dielectric film having aperture portion In the semiconductor device having a structure in which a plurality of layers are built-up by layers made of different materials or layers including various formed patterns, it is an object to provide a method which smoothing surface can be achieved without a polish... | 01/06/2009 |
| 7474003 | Semiconductor integrated circuit device Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are dis... | 01/06/2009 |
| 7439625 | Circuit board A circuit board (A1) includes an insulative substrate (1), a conductive pad (4a) formed on the substrate, and a metal (3) bonded to the pad via a solder layer (6). The metal piece (3) has a welding portion (3 | 10/21/2008 |
| 7439623 | Semiconductor device having via connecting between interconnects A first insulating film is provided between a lower interconnect and an upper interconnect. The lower interconnect and the upper interconnect are connected to each other by way of a via formed in the first insulating film. A dummy via or an insulating slit is formed... | 10/21/2008 |
| 7432594 | Semiconductor chip, electrically connections therefor A semiconductor device has a semiconductor chip including first and second surfaces opposed to each other in a thickness direction of the semiconductor chip, wherein the first and second surfaces include first and second electrode surfaces respectively, and first an... | 10/07/2008 |
