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| Number | Title | Issue Date |
| 8188604 | Semiconductor device incorporating preventative measures to reduce cracking in exposed electrode layer A semiconductor device capable of preventing a crack from occurring in an electrode layer exposed through a through hole which is formed in a semiconductor substrate and a method of manufacturing the semiconductor device. In exemplary embodiments, a through via and ... | 05/29/2012 |
| 8183696 | Packaged semiconductor device with encapsulant embedding semiconductor chip that includes contact pads A semiconductor package includes a semiconductor chip, an encapsulant embedding the semiconductor chip, first contact pads on a first main face of the semiconductor package and second contact pads on a second main face of the semiconductor package opposite to the fi... | 05/22/2012 |
| 8178977 | Semiconductor device and method of manufacturing the same When a through-hole electrode and a rear-surface wire are formed on a rear surface of a chip, a convex portion is formed on the rear surface of the chip due to a rear-surface wiring pad which is a part of the through-hole electrode and the rear-surface wire. This ca... | 05/15/2012 |
| 8178976 | IC device having low resistance TSV comprising ground connection A semiconductor device includes an integrated circuit (IC) die including a substrate, and at least one through substrate via (TSV) that extends through the substrate to a protruding integral tip that includes sidewalls and a distal end. The protruding integral tip h... | 05/15/2012 |
| 8174125 | Manufacturing method of a semiconductor device A manufacturing method of a semiconductor device comprises: providing a first insulating film whose relative dielectric constant is at most a predetermined value above a substrate; providing a second insulating film whose relative dielectric constant is greater than... | 05/08/2012 |
| 8164196 | Semiconductor device and method for manufacturing the same A semiconductor device includes a substrate, a low dielectric constant layer formed on the substrate, a first protection insulating layer formed on the low dielectric constant layer, and a trench with an interconnect embedded in formed in the first protection insula... | 04/24/2012 |
| 8159074 | Chip structure A semiconductor chip includes first, second and third metal interconnects and an insulating layer over a semiconductor substrate. First, second and third openings in the insulating layer are over first, second and third contact points of the first, second and third ... | 04/17/2012 |
| 8159071 | Semiconductor package with a metal post Disclosed are a semiconductor package and a manufacturing method thereof. The semiconductor package can include a semiconductor substrate, having one surface on which a conductive pad is formed; an insulating layer, being formed on one surface of the semiconductor s... | 04/17/2012 |
| 8159072 | Rectification chip terminal structure The present invention includes a base, a rectification chip, a conductive element and a coupling collar. The base has an installation pedestal to hold the rectification chip. The conductive element has a root portion to hold the rectification chip. The coupling coll... | 04/17/2012 |
| 8159073 | Interposer chip and manufacturing method thereof The interposer chip includes a chip mounting region on which a semiconductor chip is mounted via a fixing material made of resin. The interposer chip has an insulator film, and wiring layers formed on the insulator film. At a position corresponding to a rim of the c... | 04/17/2012 |
| 8154134 | Packaged electronic devices with face-up die having TSV connection to leads and die pad A packaged electronic device includes a leadframe including a die pad, a first, second, and third lead pin surrounding the die pad. An IC die is assembled in a face-up configuration on the lead frame. The IC die includes a substrate having an active top surface and ... | 04/10/2012 |
| 8154135 | Stacked semiconductor package A stacked semiconductor package is presented which includes multiple semiconductor chips and through-electrodes. Each semiconductor chip has bonding pads formed on a first surface of the semiconductor chip and has a projection which projects from a portion of a seco... | 04/10/2012 |
| 8154133 | Semiconductor device having low dielectric constant film and manufacturing method thereof A low dielectric constant film/wiring line stack structure made up of a stack of low dielectric constant films and wiring lines is provided in a region on the upper surface of the semiconductor substrate except for the peripheral part of this surface. The peripheral... | 04/10/2012 |
| 8154136 | Method of fabricating semiconductor device Method of fabricating thin-film transistors in which contact with connecting electrodes becomes reliable. When contact holes are formed, the bottom insulating layer is subjected to a wet etching process, thus producing undercuttings inside the contact holes. In orde... | 04/10/2012 |
| 8148824 | Semiconductor device with through substrate via A through substrate via having a low stress is provided. The through substrate via is positioned in a substrate. The through substrate via includes: an outer tube penetrating the substrate; at least one inner tube disposed within the outer tube; a dielectric layer l... | 04/03/2012 |
| 8143725 | Semiconductor device A semiconductor device includes a first interconnect 31; a second interconnect 32 which is formed in a different interconnect layer from that of the first interconnect 31, and which has a wider line width than that of the first interconnect 3... | 03/27/2012 |
| 8134235 | Three-dimensional semiconductor device A three-dimensional semiconductor device using redundant bonding-conductor structures to make inter-level electrical connections between multiple semiconductor chips. A first chip, or other semiconductor substrate, forms a first active area on its upper surface, and... | 03/13/2012 |
| 8115318 | Semiconductor device having silicon-diffused metal wiring layer and its manufacturing method In a semiconductor device, an insulating interlayer having a groove is formed on an insulating underlayer. A silicon-diffused metal layer including no metal silicide is buried in the groove. A metal diffusion barrier layer is formed on the silicon-diffused metal lay... | 02/14/2012 |
| 8115317 | Semiconductor device including electrode structure with first and second openings and manufacturing method thereof To improve connection reliability of a through electrode in a semiconductor device, and prevent deterioration of electrical characteristics due to a residue generated from a pad at the time of forming the through electrode. A contact area between a pad and a conduct... | 02/14/2012 |
| 8115316 | Packaging board, semiconductor module, and portable apparatus A technology is provided for a packaging board adapted to mount a device capable of improving handleability and securing connection reliability. The packaging board includes: a pad electrode formed on a substrate; an insulating layer covering the substrate, having a... | 02/14/2012 |
| 8110927 | Explosion-proof module structure for power components, particularly power semiconductor components, and production thereof A power module having at least one electric power component, such as a power electronic semiconductor component. An electrical contact for a load current is formed on a lower surface and also on an upper surface of the power semiconductor component. To reduce an exp... | 02/07/2012 |
| 8106518 | Semiconductor device and method of manufacturing the same In a semiconductor device in which a plurality of semiconductor chips are stacked, performance is enhanced without deteriorating productivity. The semiconductor device has a plurality of elements, an interlayer insulating film, a pad, and a bump electrode electrical... | 01/31/2012 |
| 8102056 | Semiconductor device having pads and which minimizes defects due to bonding and probing processes A semiconductor device includes: a semiconductor substrate; a first interlayer insulating film formed over the semiconductor substrate; a pad formed above the first interlayer insulating film; and a plurality of first interconnects spaced apart from each other in a ... | 01/24/2012 |
| 8102057 | Via design for flux residue mitigation Provided is an electrically conductive via for reducing flux residue. The via has a first aperture having a first diameter size. The via further has a second aperture having a second diameter size. A chamber is disposed between the first aperture and the second aper... | 01/24/2012 |
| 8102058 | Chip package structure and method for fabricating the same The disclosure provides a chip package structure and method for fabricating the same. The chip package structure includes at least one chip having at least one through via. At least one stress buffering structure is disposed in the through via. The stress buffering ... | 01/24/2012 |
| 8097953 | Three-dimensional integrated circuit stacking-joint interface structure A system, a structure and a method of manufacturing stacked semiconductor substrates is presented. A first substrate includes a first side and a second side. A through substrate via (TSV) protrudes from the first side of the first substrate. A first protruding porti... | 01/17/2012 |
| 8095905 | Power supply wiring structure Provided is a power supply wiring structure which comprises a first and a second power supply wirings, which are disposed on different planes to cross each other two-dimensionally. The first and second power supply wirings are interlayer-connected by a first via at ... | 01/10/2012 |
| 8093725 | High aspect ratio contacts A contact formed in accordance with a process for etching a insulating layer to produce an opening having an aspect ratio of at least 15:1 by first exposing the insulating layer to a second plasma of a second gaseous etchant comprising Ar, Xe, and combinations there... | 01/10/2012 |
| 8089162 | Semiconductor device and method for manufacturing the same In a pad forming region electrically connecting an element forming region to the outside, in which a low dielectric constant insulating film is formed in association with in the element forming region, a Cu film serving as a via formed in the low dielectric constant... | 01/03/2012 |
| 8089160 | IC interconnect for high current An IC interconnect according to one embodiment includes a first via positioned in a dielectric and coupled to a high current device at one end; a buffer metal segment positioned in a dielectric and coupled to a top portion of the first via; and a plurality of second... | 01/03/2012 |
| 8089161 | Semiconductor device and method of manufacturing the same A semiconductor device has a substrate, an insulating interlayer, an interconnect as one example of an electro-conductive pattern, a through-electrode, and a bump as one example of a connection terminal, wherein the insulating interlayer is positioned up above the s... | 01/03/2012 |
| 8084866 | Microelectronic devices and methods for filling vias in microelectronic devices Microelectronic devices and methods for filling vias and forming conductive interconnects in microfeature workpieces and dies are disclosed herein. In one embodiment, a method includes providing a microfeature workpiece having a plurality of dies and at least one pa... | 12/27/2011 |
| 8084867 | Apparatus, system, and method for wireless connection in integrated circuit packages Some embodiments of the invention include a connecting structure between a support and at least one die attached to the support. The die includes a number of die bond pads on a surface of the die. The connecting structure includes a plurality of via and groove combi... | 12/27/2011 |
| 8080882 | Semiconductor device and method of forming stepped-down RDL and recessed THV in peripheral region of the device A semiconductor die has a peripheral region around the die. An insulating layer is formed over the semiconductor die. A portion of the insulating layer and peripheral is removed to form a recess around the semiconductor die. A conductive layer is deposited over the ... | 12/20/2011 |
| 8080881 | Contact pad supporting structure and integrated circuit for crack suppresion The invention provides a contact pad supporting structure. The contact pad supporting structure includes an underlying first conductive plate and an overlying second conductive plate, wherein the first and second conductive plates are separated by a first dielectric... | 12/20/2011 |
| 8076782 | Substrate for mounting IC chip An object of the present invention is to provide a substrate for mounting an IC chip which is a component for optical communication having an IC chip and an optical component integrally provided thereon, which can ensure a short distance between the IC chip and the ... | 12/13/2011 |
| 8076783 | Memory devices having contact features Annular, linear, and point contact structures are described which exhibit a greatly reduced susceptibility to process deviations caused by lithographic and deposition variations than does a conventional circular contact plug. In one embodiment, a standard conductive... | 12/13/2011 |
| 8072079 | Through hole vias at saw streets including protrusions or recesses for interconnection A semiconductor package includes a semiconductor die having a contact pad formed over a top surface of the semiconductor die. The semiconductor die may include an optical device. In one embodiment, a second semiconductor die is deposited over the semiconductor die. ... | 12/06/2011 |
| 8067839 | Stacked semiconductor package and method for manufacturing the same Disclosed are a stacked semiconductor package and a method for manufacturing the same. The method for manufacturing a stacked semiconductor package includes preparing a substrate formed with a seed metal layer; laminating semiconductor chips having via holes aligned... | 11/29/2011 |
| 8058732 | Semiconductor die structures for wafer-level chipscale packaging of power devices, packages and systems for using the same, and methods of making the same Disclosed are semiconductor die structures that enable a die having a vertical power device to be packaged in a wafer-level chip scale package where the current-conducting terminals are present at one surface of the die, and where the device has very low on-state re... | 11/15/2011 |
