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| Number | Title | Issue Date |
| 8183695 | Semiconductor device and method of manufacturing the same A semiconductor chip includes a semiconductor chip region provided with a plurality of internal circuits, and a plurality of electrode pads provided proximate to an outer edge of the semiconductor chip region and each electrically connected to any one of the plurali... | 05/22/2012 |
| 8178975 | Semiconductor package with pad parts electrically connected to bonding pads through re-distribution layers The semiconductor package includes: a semiconductor chip module having multiple adjacently arranged or integrally formed semiconductor chips each with a bonding pad group and a connection member electrically connecting each of the bonding pads included in the first ... | 05/15/2012 |
| 8178974 | Microstrip structure including a signal line with a plurality of slit holes A semiconductor device comprising a signal transmission line of a microstrip structure, capable of increasing the characteristic impedance of the signal transmission line and reducing coupling between a plurality of signal lines. In a signal transmission line of a m... | 05/15/2012 |
| 8174123 | Semiconductor integrated circuit A semiconductor integrated circuit according to an exemplary embodiment of the present invention includes an I/O buffer provided in a semiconductor chip, single-layer pads, and multilayer pads. The single-layer pads are formed above the I/O buffer. The multilayer pa... | 05/08/2012 |
| 8174124 | Dummy pattern in wafer backside routing A device includes a semiconductor substrate including a front side and a backside. A through-substrate via (TSV) penetrates the semiconductor substrate. A dummy metal line is formed on the backside of the semiconductor substrate, and may be connected to the dummy TS... | 05/08/2012 |
| 8169081 | Conductive routings in integrated circuits using under bump metallization An integrated circuit structure includes a first conductive layer and an under bump metallization layer over the first conductive layer. The first conductive layer has a first conductive region and a second conductive region electrically isolated from the first cond... | 05/01/2012 |
| 8164194 | Data line structure in lead region An embodiment of the invention provides a data line structure in a lead region of a thin film transistor liquid crystal display (TFT-LCD). The data line structure in the lead region comprises a substrate and a gate layer data line segment, a dielectric layer, a data... | 04/24/2012 |
| 8164195 | Pad structure of semiconductor integrated circuit apparatus A pad structure of a semiconductor integrated circuit apparatus includes a semiconductor substrate upon which circuit patterns forming a device are disposed, a pad disposed on an uppermost part of the semiconductor substrate, and a plurality of fixing parts, each di... | 04/24/2012 |
| 8154131 | Profiled contact A semiconductor chip, having IC pads, the semiconductor chip having a device, electrically connected to at least one electrical contact through the IC pad, the electrical contact having a height and a cross sectional profile, through the height, configured to facili... | 04/10/2012 |
| 8154132 | Semiconductor device comprising internal and external wiring A semiconductor device of the invention include a rectangular semiconductor element mounted on a substrate formed with an external input terminal, an external output terminal, and a plurality of wiring patterns connected to each of the external input terminal and th... | 04/10/2012 |
| 8148823 | Low loss package for electronic device A package for one or more semiconductor die is described. A generally rectangular package includes two large terminals that occupy substantially the entire length of the package and provide low resistance connections. Additional connections may be provided preferabl... | 04/03/2012 |
| 8138607 | Metal fill structures for reducing parasitic capacitance Vertically-staggered-level metal fill structures include inner contiguous metal fill structures and outer contiguous metal fill structures. A dielectric material portion is provided between each contiguous metal fill structure. Vertical extent of each contiguous met... | 03/20/2012 |
| 8138609 | Semiconductor device and method of manufacturing semiconductor device In a semiconductor device, a substrate includes a plurality of line conductors which penetrate the substrate from a top surface to a bottom surface of the substrate. A semiconductor chip is secured in a hole of the substrate. A first insulating layer is formed on th... | 03/20/2012 |
| 8138608 | Integrated circuit package substrate having configurable bond pads Methods, systems, and apparatuses for integrated circuit package substrates, integrated circuit packages, and processes for assembling the same, are provided. A substrate for a flip chip integrated circuit package includes a substrate body having opposing first and ... | 03/20/2012 |
| 8115314 | Deep contacts of integrated electronic devices based on regions implanted through trenches An embodiment of an integrated circuit includes first and second semiconductor layers and a contact region disposed in the second layer. The first semiconductor layer is of a first conductivity, and the second semiconductor layer is disposed over the first layer and... | 02/14/2012 |
| 8115315 | Semiconductor chips having redistributed power/ground lines directly connected to power/ground lines of internal circuits and methods of fabricating the same Provided are embodiments of semiconductor chips having a redistributed metal interconnection directly connected to power/ground lines of an internal circuit are provided. Embodiments of the semiconductor chips include an internal circuit formed on a semiconductor su... | 02/14/2012 |
| 8110926 | Redistribution layer power grid An integrated circuit package including a first metal layer coupled to a bonding pad, a first redistribution layer coupled to the bonding pad, and a RDL to Metal (RTM) via coupled to a first surface of the metal layer and further coupled to a first surface of the fi... | 02/07/2012 |
| 8106517 | Connecting and bonding adjacent layers with nanostructures An apparatus, comprising two conductive surfaces or layers and a nanostructure assembly bonded to the two conductive surfaces or layers to create electrical or thermal connections between the two conductive surfaces or layers, and a method of making same. ... | 01/31/2012 |
| 8102055 | Semiconductor device A semiconductor device including a semiconductor chip, a base substrate, a wiring positioned on the base substrate, and a eutectic alloy. A part of the eutectic alloy is positioned between the wiring and the base substrate. ... | 01/24/2012 |
| 8102054 | Reliable interconnects A method for forming a semiconductor device is presented. The method includes providing a substrate prepared with a dielectric layer formed thereon. The dielectric layer having a conductive line disposed in an upper portion of the dielectric layer. The substrate is ... | 01/24/2012 |
| 8097951 | Integrated circuit having wiring layer and a pattern in which a gap is formed and method for manufacturing same When an integrated circuit having an interlayer insulation film built up on top of a wiring layer is subjected to a heat treatment, it is unlikely that a void formed in the interlayer insulation film will rupture in a portion wherein are connected a narrow gap betwe... | 01/17/2012 |
| 8097952 | Electronic package structure having conductive strip and method An electronic package structure and method use a conductive strip to bond die-to-die, die-to-lead, chip carrier-to-lead, or lead-to-lead. A conductive strip may carry greater current than a bonding wire, and thus may replace several bonding wires. The bonding of the... | 01/17/2012 |
| 8097950 | Semiconductor device and electronic component module using the same A semiconductor device includes a circuit board having an element mounting area, connecting pads positioned in the same surface side as the element mounting area and external connectors to be connected with the connecting pads, respectively; and a semiconductor elem... | 01/17/2012 |
| 8093724 | Semiconductor storage device a semiconductor storage device is provided with a plurality of active regions formed in the shape of a band in a semiconductor substrate; a plurality of word lines arranged at equal intervals so as to intersect the active regions; a plurality of cell contacts that i... | 01/10/2012 |
| 8089159 | Semiconductor package with increased I/O density and method of making the same The present invention is related to a semiconductor package and method for fabricating the same wherein the semiconductor package includes a die pad having a semiconductor die mounted thereto, and two or more sets of leads or I/O pads which extend at least partially... | 01/03/2012 |
| 8084865 | Anchoring structure and intermeshing structure An anchoring structure for a metal structure of a semiconductor device includes an anchoring recess structure having at least one overhanging side wall, the metal structure being at least partly arranged within the anchoring recess structure. ... | 12/27/2011 |
| 8080880 | Semiconductor device with arrangement of parallel conductor lines being insulated, between and orthogonal to external contact pads A semiconductor device and manufacturing method. One embodiment provides a device including a semiconductor chip. A first conductor line is placed over the semiconductor chip. An external contact pad is placed over the first conductor line. At least a portion of the... | 12/20/2011 |
| 8072078 | Semiconductor device and dummy pattern arrangement method A semiconductor device includes a plurality of wiring patterns arranged in a first wiring layer of the semiconductor device and extending in a first direction, and a plurality of dummy patterns arranged in the first wiring layer and extending in a second direction d... | 12/06/2011 |
| 8072077 | Semiconductor memory device Disclosed herein is a semiconductor memory device for reducing a junction resistance and increasing amount of current throughout the unit cell. A semiconductor memory device comprises plural unit cells, each coupled to contacts formed in different shape at both side... | 12/06/2011 |
| 8063490 | Semiconductor device including semiconductor constituent A semiconductor device includes a semiconductor constituent having a semiconductor substrate and a plurality of electrodes for external connection provided under the semiconductor substrate. An under-layer insulating film is provided under and around the semiconduct... | 11/22/2011 |
| 8053898 | Connection for off-chip electrostatic discharge protection A method and apparatus for off-chip ESD protection, the apparatus includes an unprotected IC 22 stacked on an ESD protection chip 24 and employing combinations of edge wrap 32 and through-silicon via connectors 44 for electrical connectio... | 11/08/2011 |
| 8053897 | Production of a carrier wafer contact in trench insulated integrated SOI circuits having high-voltage components The invention relates to a method for producing structures which make it possible to form a trench insulation and to bring into contact SOI wafers provided with active thick layers and which are easily processable. For this purpose, a carrier wafer electric contact ... | 11/08/2011 |
| 8049337 | Substrate and manufacturing method of package structure A substrate board and a manufacturing method of a package structure are provided. The substrate board includes a first surface, a die-attaching area, a cutting area, a plurality of first pads and a first solder mask. The die-attaching area for attaching a die is loc... | 11/01/2011 |
| 8044517 | Electronic component comprising predominantly organic functional materials and a method for the production thereof An electronic component comprises a plurality of layers at least two of which comprise predominantly organic functional materials with improved through-plating through certain of the layers. The through-plating is formed in one embodiment by a disruption element on ... | 10/25/2011 |
| 8044518 | Junction member comprising junction pads arranged in matrix and multichip package using same A second semiconductor chip and a junction member are mounted on a first semiconductor chip formed with a plurality of first pads on a surface thereof. A resin encapsulating body is provided which seals the first semiconductor chip, the second semiconductor chip and... | 10/25/2011 |
| 8039965 | Semiconductor device with reduced layout area having shared metal line between pads A semiconductor device with a reduced layout area includes pads disposed between a first voltage line and a second voltage line; first and second driver units adjacently disposed at an upper portion or a lower portion of the respective pads; and a metal line dispose... | 10/18/2011 |
| 8039966 | Structures of and methods and tools for forming in-situ metallic/dielectric caps for interconnects A structure, tool and method for forming in-situ metallic/dielectric caps for interconnects. The method includes forming wire embedded in a dielectric layer on a semiconductor substrate, the wire comprising a copper core and an electrically conductive liner on sidew... | 10/18/2011 |
| 8039964 | Fluorine depleted adhesion layer for metal interconnect structure A line trough and a via cavity are formed within a dielectric layer comprising a fluorosilicate glass (FSG) layer. A fluorine depleted adhesion layer is formed within the line trough and the via cavity either by a plasma treatment that removes fluorine from exposed ... | 10/18/2011 |
| 8039967 | Wiring substrate with a wire terminal A wiring substrate includes a silicon substrate, a through hole formed to penetrate the silicon substrate in a thickness direction, an insulating layer formed on both surfaces and side surfaces of the silicon substrate and an inner surface of the through hole, a pen... | 10/18/2011 |
| 8035229 | Semiconductor device A semiconductor device includes: a gate electrode formed above a semiconductor region; a drain region and a source region formed in portions of the semiconductor region located below sides of the gate electrode in a gate length direction, respectively; a plurality o... | 10/11/2011 |
