Quotables
"To place a man in a multi-stage rocket and project him into the controlling gravitational field of the moon where the passengers can make scientific observations, perhaps land alive, and then return to earth--all that constitutes a wild dream worthy of Jules Verne. I am bold enough to say that such a man-made voyage will never occur regardless of all future advances."
Lee deForest, American radio pioneer ; 1957
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| Number | Title | Issue Date |
| 7830016 | Seed layer for reduced resistance tungsten film Briefly, a memory device comprising a beta phase tungsten seed layer is disclosed. ... | 11/09/2010 |
| 7485965 | Through via in ultra high resistivity wafer and related methods A through via in an ultra high resistivity wafer and related methods are disclosed. A method for forming a through via comprises: providing a semiconductor wafer including a first silicon layer, a buried dielectric layer, and a substrate; forming a device on the fir... | 02/03/2009 |
| 7443032 | Memory device with chemical vapor deposition of titanium for titanium silicide contacts A titanium layer is formed on a substrate with chemical vapor deposition (CVD). First, a seed layer is formed on the substrate by combining a first precursor with a reducing agent by CVD. Then, the titanium layer is formed on the substrate by combining a second prec... | 10/28/2008 |
| 7385260 | Semiconductor device having silicide thin film and method of forming the same The present invention provides a semiconductor device having a silicide thin film and method of forming the same. A semiconductor device comprises a gate insulation layer formed on an active region of a semiconductor substrate. A gate electrode is formed on the gate... | 06/10/2008 |
| 7372160 | Barrier film deposition over metal for reduction in metal dishing after CMP A protective barrier layer, formed of a material such as titanium or titanium nitride for which removal by chemical mechanical polishing (CMP) is primarily mechanical rather than primarily chemical, formed on a conformal tungsten layer. During subsequent CMP to patt... | 05/13/2008 |
| 7341906 | Method of manufacturing sidewall spacers on a memory device, and device comprising same The present invention is generally directed to a method of manufacturing sidewall spacers on a memory device, and a memory device comprising such sidewall spacers. In one illustrative embodiment, the method includes forming sidewall spacers on a memory device compri... | 03/11/2008 |
| 7312531 | Semiconductor device and fabrication method thereof Semiconductor devices and methods for fabricating the same. The devices include a substrate, a catalyst layer, a second dielectric layer, and carbon nanotubes (CNTs). The substrate comprises an overlying first dielectric layer with an electrode embedded therein. The... | 12/25/2007 |
| 7294893 | Titanium silicide boride gate electrode A method for use in the fabrication of a gate electrode includes providing a gate oxide layer and forming a titanium boride layer on the oxide layer. An insulator cap layer is formed on the titanium boride layer and thereafter, the gate electrode is formed from the ... | 11/13/2007 |
| 7294565 | Method of fabricating a wire bond pad with Ni/Au metallization A method for sealing an exposed surface of a wire bond pad with a material that is capable of preventing a possible chemical attack during electroless deposition of Ni/Au pad metallurgy is provided. Specifically, the present invention provides a method whereby a TiN... | 11/13/2007 |
| 7256501 | Semiconductor device and manufacturing method of the same In a semiconductor device having a package structure in which lead terminals connected to electrodes on both of the upper and lower surfaces of a semiconductor chip are exposed from both of the upper and lower surfaces and side surfaces of a sealing body formed of r... | 08/14/2007 |
| 7245018 | Wiring material, semiconductor device provided with a wiring using the wiring material and method of manufacturing thereof A semiconductor device having good TFT characteristics is realized. By using a high purity target as a target, using a single gas, argon (Ar), as a sputtering gas, setting the substrate temperature equal to or less than 300° C., and setting the sputtering gas press... | 07/17/2007 |
| 7179743 | Titanium underlayer for lines in semiconductor devices A thin Titanium underlayer 22 is included beneath a Titanium rich Titanium Nitride layer 28 in a metal line 20 on a silicon substrate to reduce stress voiding. ... | 02/20/2007 |
| 7170174 | Contact structure and contact liner process A contact structure and a method of forming thereof for semiconductor devices or assemblies are described. The method provides process steps to create a contact structure encompassed by a sacrificial contact medium having an opening therein that is lined with a cond... | 01/30/2007 |
| 7161211 | Aluminum-containing film derived from using hydrogen and oxygen gas in sputter deposition Aluminum-containing films having an oxygen content within the films. The aluminum-containing film is formed by introducing hydrogen gas along with argon gas into a sputter deposition vacuum chamber during the sputter deposition of aluminum or aluminum alloys onto a ... | 01/09/2007 |
| 7148570 | Low resistivity titanium silicide on heavily doped semiconductor Low resistivity, C54-phase TiSi2 is formed in narrow lines on heavily doped polysilicon by depositing a bi-layer silicon film. A thin, undoped amorphous layer is deposited on top of a heavily doped layer. The thickness of the undoped amorphous Si is about... | 12/12/2006 |
| 7129531 | Programmable resistance memory element with titanium rich adhesion layer A programmable resistance memory element comprising an adhesion layer between the programmable resistance material and at least one of the electrodes. Preferably, the adhesion layer is a titanium rich titanium nitride composition. ... | 10/31/2006 |
| 7122903 | Contact plug processing and a contact plug A semiconductor device has anisotropically formed via holes through a PMD layer. The anisotropic geometry of the via holes results in the diameter of a via hole over a gate structure being equal to the diameter of a via hole not over the gate structure. The via hole... | 10/17/2006 |
| 7119443 | Semiconductor integrated circuit device having a conductive film which contains metal atoms bondable to a halogen element The semiconductor device is formed according to the following steps. A TiN film 71 and a W film 72 are deposited on a silicon oxide film 64 including the inside of a via-hole 66 by the CVD method and thereafter, the W film 72 and T... | 10/10/2006 |
| 7115993 | Structure comprising amorphous carbon film and method of forming thereof A semiconductor device includes a semiconductor substrate, a film stack formed on the semiconductor substrate and having a film to be processed. A dual hard mask included in the film stack has an amorphous carbon layer and an underlying hard mask layer interposed be... | 10/03/2006 |
| 7109087 | Absorber layer for DSA processing A method of processing a substrate comprising depositing a layer comprising amorphous carbon on the substrate and then laser annealing the substrate is provided. Optionally, the layer further comprises a dopant selected from the group consisting of nitrogen, boron, ... | 09/19/2006 |
| 7098479 | Electro-optical device and method for manufacturing the same An electro-optical device and a method for manufacturing the same are disclosed. The device comprises a pair of substrates and an electro-optical modulating layer (e.g. a liquid crystal layer having sandwiched therebetween, said pair of substrates consisting of a fi... | 08/29/2006 |
| 7094657 | Method for protecting against oxidation of a conductive layer in said device In a semiconductor device including a first conductive layer, the first conductive layer is treated with a nitrogen/hydrogen plasma before an additional layer is deposited thereover. The treatment stuffs the surface with nitrogen, thereby preventing oxygen from bein... | 08/22/2006 |
| 7087997 | Copper to aluminum interlayer interconnect using stud and via liner Tungsten studs of a size comparable to vias are provided to integrate and interface between copper and aluminum metallization layers in an integrated circuit and/or package therefor by lining a via opening, preferably with layers of tantalum nitride and PVD tungsten... | 08/08/2006 |
| 7071563 | Barrier layer for interconnect structures of a semiconductor wafer and method for depositing the barrier layer An interconnect structure of a semiconductor device includes a tungsten plug (14) deposited in a via or contact window (11). A barrier layer (15) separates the tungsten plug (14) from the surface of a dielectric material (16) withi... | 07/04/2006 |
| 7067861 | Device and method for protecting against oxidation of a conductive layer in said device In a semiconductor device including a first conductive layer, the first conductive layer is treated with a nitrogen/hydrogen plasma before an additional layer is deposited thereover. The treatment stuffs the surface with nitrogen, thereby preventing oxygen from bein... | 06/27/2006 |
| 7060584 | Process to improve high performance capacitor properties in integrated MOS technology A method of fabricating a high performance capacitor that may be incorporated into a standard CMOS fabrication process suitable for submicron devices is described. The parameters used in the standard CMOS process may be maintained, particularly for the definition an... | 06/13/2006 |
| 7049191 | Method for protecting against oxidation of a conductive layer in said device In a semiconductor device including a first conductive layer, the first conductive layer is treated with a nitrogen/hydrogen plasma before an additional layer is deposited thereover. The treatment stuffs the surface with nitrogen, thereby preventing oxygen from bein... | 05/23/2006 |
| 7045831 | Semiconductor device A semiconductor device of the present invention comprises a semiconductor chip, metal layers formed on a first main surface of the semiconductor chip, a first conductive layer layered on a second main surface of the semiconductor chip, consisting of a plurality of c... | 05/16/2006 |
| 7041550 | Device and method for protecting against oxidation of a conductive layer in said device In a semiconductor device including a first conductive layer, the first conductive layer is treated with a nitrogen/hydrogen plasma before an additional layer is deposited thereover. The treatment stuffs the surface with nitrogen, thereby preventing oxygen from bein... | 05/09/2006 |
| 7033642 | Plasma enhanced chemical vapor deposition method of forming a titanium silicide comprising layer Chemical vapor deposition methods of forming titanium silicide including layers on substrates are disclosed. TiCl4 and at least one silane are first fed to the chamber at or above a first volumetric ratio of TiCl4 to silane for a first period o... | 04/25/2006 |
| 7030459 | Three-dimensional memory structure and manufacturing method thereof A three-dimensional memory structure and manufacturing method thereof is provided. A first stack layer is formed over a substrate. The first stack layer includes, from the substrate upwards, an n-type polysilicon layer, a conductive layer, an anti-fuse and another n... | 04/18/2006 |
| 7012294 | Semiconductor constructions The invention encompasses a method of forming a silicon nitride layer. A substrate is provided which comprises a first mass and a second mass. The first mass comprises silicon and the second mass comprises silicon oxide. A sacrificial layer is formed over the first ... | 03/14/2006 |
| 7005722 | RC terminator and production method therefor A thin-film RC circuit element suitable for a transmission line termination circuit is prepared by a process wherein 1) a first metal layer of an anodizable metal is deposited on a substrate; 2) the exposed surface... | 02/28/2006 |
| 6984891 | Methods for making copper and other metal interconnections in integrated circuits A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with aluminum wires. Yet, aluminum wires have greater electrical resistance and are less reliable than copper wires. Unfortunately, current techniques... | 01/10/2006 |
| 6972452 | Device and method for protecting against oxidation of a conductive layer in said device In a semiconductor device including a first conductive layer, the first conductive layer is treated with a nitrogen/hydrogen plasma before an additional layer is deposited thereover. The treatment stuffs the surface with nitrogen, thereby preventing oxygen from bein... | 12/06/2005 |
| 6953996 | Low-loss coplanar waveguides and method of fabrication Coplanar waveguides having a deep trench between a signal line and a ground plane and methods of their fabrication are disclosed. An oxide layer is provided over a silicon substrate and a photoresist is applied and patterned to define areas where the signal line and... | 10/11/2005 |
| 6949833 | Combined atomic layer deposition and damascene processing for definition of narrow trenches The invention offers a structure that includes a substrate with a top surface and a bottom surface, an etched dielectric layer having sidewalls and an upper surface, wherein the etched dielectric layer with a thickness of v, is positioned upon a first portion of the... | 09/27/2005 |
| 6940094 | Electronic device and method for manufacturing the same An electronic device is provided using wiring comprising aluminum to prevent hillock or whisker from generating, wherein the wiring contains oxygen atoms at a concentration of 8×1018 atoms·cm−3 or less, carbon atoms at a concentration of 5Ã... | 09/06/2005 |
| 6940172 | Chemical vapor deposition of titanium A titanium layer is formed on a substrate with chemical vapor deposition (CVD). First, a seed layer is formed on the substrate by combining a first precursor with a reducing agent by CVD. Then, the titanium layer is formed on the substrate by combining a second prec... | 09/06/2005 |
| 6930029 | Method of passivating an oxide surface subjected to a conductive material anneal A method of preventing formation of titanium oxide within a semiconductor device structure during a high temperature treatment of the device structure includes forming a passivation layer to preclude formation of titanium oxide at a titanium/oxide interface of a sem... | 08/16/2005 |
