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| Number | Title | Issue Date |
| 7709961 | Implantable microelectronic device and method of manufacture An implantable hermetically sealed microelectronic device and method of manufacture are disclosed. The microelectronic device of the present invention is hermetically encased in a insulator, such as alumina formed by ion bean assisted deposition (“IBAD”), with a... | 05/04/2010 |
| 7701062 | Semiconductor device and method for producing the same Provided, is a reliable semiconductor device with a layered interconnect structure that may develop no trouble of voids and interconnect breakdowns, in which the layered interconnect structure comprises a conductor film and a neighboring film as so layered on a semi... | 04/20/2010 |
| 7436067 | Methods for forming conductive structures and structures regarding same A method for forming a metal/metal oxide structure that includes forming metal oxide regions, e.g., ruthenium oxide regions, at grain boundaries of a metal layer, e.g., platinum. Preferably, the metal oxide regions are formed by diffusion of oxygen through grain bou... | 10/14/2008 |
| 7400042 | Substrate with adhesive bonding metallization with diffusion barrier A metallization layer that includes a tantalum layer located on the component, a tantalum silicide layer located on the tantalum layer, and a platinum silicide layer located on the tantalum silicide layer. In another embodiment the invention is a component having a ... | 07/15/2008 |
| 7372152 | Copper interconnect systems An integrated circuit (IC) may include a substrate, a first dielectric layer adjacent the substrate, and at least one trench in the first dielectric layer. The IC may also include a metal liner within the at least one trench, and a first conductive region including ... | 05/13/2008 |
| 7348265 | Semiconductor device having a silicided gate electrode and method of manufacture therefor The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the semiconductor device. The semiconductor device (100), among other possible elements, includes a gate oxide (140) located ov... | 03/25/2008 |
| 7319270 | Multi-layer electrode and method of forming the same An interconnect includes an opening formed in a dielectric layer. A conductive barrier is deposited in the opening, over which a first conductive layer is deposited. A conductive oxide is deposited over the first conductive layer, and a second conductive layer, form... | 01/15/2008 |
| 7295029 | Chip-scale package for integrated circuits A chip-scale packaged IC is made by bonding one or more singulated die chips (from an IC wafer) to a common substrate, such as a single cap wafer (or a portion thereof) and cutting (singulating) the substrate to yield individual, chip-scale packaged ICs. Alternative... | 11/13/2007 |
| 7262622 | Wafer-level package for integrated circuits A wafer-level packaged IC is made by attaching a cap wafer to the top of an IC wafer before cutting the IC wafer, i.e. before singulating the plurality of die on the IC wafer. The cap wafer is mechanically attached and electrically connected to the IC wafer, then th... | 08/28/2007 |
| 7256501 | Semiconductor device and manufacturing method of the same In a semiconductor device having a package structure in which lead terminals connected to electrodes on both of the upper and lower surfaces of a semiconductor chip are exposed from both of the upper and lower surfaces and side surfaces of a sealing body formed of r... | 08/14/2007 |
| 7247915 | Cobalt/nickel bi-layer silicide process for very narrow line polysilicon gate technology A silicide method for integrated circuit and semiconductor device fabrication wherein a layer of nickel is formed over at least one silicon region of a substrate and a layer of cobalt is formed over the nickel layer. The cobalt/nickel bi-layer is then annealed to tr... | 07/24/2007 |
| 7244973 | Field-effect semiconductor device and method for making the same A method for making a filed-effect semiconductor device includes the steps of forming a gate electrode on a semiconductor layer composed of a gallium nitride-based compound semiconductor represented by the formula AlxInyGa1−x−yN,... | 07/17/2007 |
| 7208414 | Method for enhanced uni-directional diffusion of metal and subsequent silicide formation The present invention provides a method for enhancing uni-directional diffusion of a metal during silicidation by using a metal-containing silicon alloy in conjunction with a first anneal in which two distinct thermal cycles are performed. The first thermal cycle of... | 04/24/2007 |
| 7115997 | Seedless wirebond pad plating An integrated circuit (IC) chip, semiconductor wafer with IC chips in a number of die locations and a method of making the IC chips on the wafer. The IC chips have plated chip interconnect pads. Each plated pad includes a noble metal plated layer electroplated to a ... | 10/03/2006 |
| 7105439 | Cobalt/nickel bi-layer silicide process for very narrow line polysilicon gate technology A silicide method for integrated circuit and semiconductor device fabrication wherein a layer of nickel is formed over at least one silicon region of a substrate and a layer of cobalt is formed over the nickel layer. The cobalt/nickel bi-layer is then annealed to tr... | 09/12/2006 |
| 7081676 | Structure for controlling the interface roughness of cobalt disilicide A method of producing electrical contacts having reduced interface roughness as well as the electrical contacts themselves are disclosed herein. The method of the present invention comprises (a) forming an alloy layer having the formula MX, wherein M is a metal sele... | 07/25/2006 |
| 7053462 | Planarization of metal container structures A conductive material is provided in an opening formed in an insulative material. The process involves first forming a conductive material over at least a portion of the opening and over at least a portion of the insulative material which is outside of the opening. ... | 05/30/2006 |
| 7038306 | Semiconductor integrated circuit device and method of manufacturing the same A semiconductor integrated circuit device is provided which includes a wire having a diameter equal to or less than 30 μm, and a connected member molded by a resin. The connected member includes a metal layer including a palladium layer provided at a portion to whi... | 05/02/2006 |
| 7030493 | Semiconductor device having layered interconnect structure with a copper or platinum conducting film and a neighboring film Provided is a reliable semiconductor device with a layered interconnect structure that may develop no trouble of voids and interconnect breakdowns, in which the layered interconnect structure comprises a conductor film and a neighboring film as so layered on a semic... | 04/18/2006 |
| 7026714 | Copper interconnect systems which use conductive, metal-based cap layers An integrated circuit (IC) may include a substrate, a first dielectric layer adjacent the substrate, and at least one trench in the first dielectric layer. The IC may also include a metal liner within the at least one trench, and a first conductive region including ... | 04/11/2006 |
| 7012312 | Semiconductor device with multilayer conductive structure formed on a semiconductor substrate A highly reliable semiconductor device having a multilayer structure including an insulating film, an adjacent conductive film, and a main conductive film in which adhesive fractures, voids and disconnections are unlikely to occur. Regarding main constituent element... | 03/14/2006 |
| 7009279 | Semiconductor device configured for suppressed germanium diffusion from a germanium-doped regions and a method for fabrication thereof In semiconductor devices, a semiconductor device is provided which is high in reliability while suppressing changes in characteristics such as threshold voltages. In a semiconductor device which has a gate dielectric film above a semiconductor substrate and also has... | 03/07/2006 |
| 6998714 | Selectively coating bond pads Solder ball bond pads and wire bond pads may be selectively coated so that the wire bond bond pads have a thicker gold coating than the solder ball bond pads. This may reduce the embrittlement of solder ball joints while providing a sufficient thickness of gold for ... | 02/14/2006 |
| 6979862 | Trench MOSFET superjunction structure and method to manufacture A power semiconductor device including a plurality of trenches each for supporting a gate structure adjacent a channel region, and a plurality of drain columns each under the bottom of each trench, and each formed by multiple high energy implants. ... | 12/27/2005 |
| 6917112 | Conductive semiconductor structures containing metal oxide regions A method for forming a metal/metal oxide structure that includes forming metal oxide regions, e.g.. ruthenium oxide regions, at grain boundaries of a metal layer, e.g., platinum. Preferably, the metal oxide regions are formed by diffusion of oxygen through grain bou... | 07/12/2005 |
| 6914336 | Semiconductor device structure and method for manufacturing the same The present invention provides a structure for a semiconductor device, capable of eliminating the generation of defective products due to poor connection. In the present semiconductor device, an n-type high concentration diffusion layer 2 is selectively forme... | 07/05/2005 |
| 6906417 | Ball grid array utilizing solder balls having a core material covered by a metal layer A ball grid array for a flip-chip assembly. The ball grid array includes a plurality of bumps bonded between an active surface of a semiconductor die and a top surface of a printed circuit board or any type of substrate carrier. The plurality of balls include at lea... | 06/14/2005 |
| 6870203 | Field-effect semiconductor device and method for making the same A method for making a filed-effect semiconductor device includes the steps of forming a gate electrode on a semiconductor layer composed of a gallium nitride-based compound semiconductor represented by the formula AlxInyGa1-x-yN, whe... | 03/22/2005 |
| 6867130 | Enhanced silicidation of polysilicon gate electrodes Semiconductor devices exhibiting reduced gate resistance and reduced silicide spiking in source/drain regions are fabricated by forming thin metal silicide layers on the gate electrode and source/drain regions and then selectively resilicidizing the gate electrodes.... | 03/15/2005 |
| 6822307 | Semiconductor triode device having a compound-semiconductor channel layer A semiconductor triode comprises a gate electrode provided on a channel layer, wherein there is interposed an insulating metal oxide layer between a top surface of the channel layer and the gate electrode. ... | 11/23/2004 |
| 6806573 | Low angle, low energy physical vapor deposition of alloys An alloy or composite is deposited in a recess feature of a semiconductor substrate by sputtering an alloy or composite target into a recess, to form a first layer of deposited material. The first layer of deposited material is resputtered at a low angle and low ene... | 10/19/2004 |
| 6787833 | Integrated circuit having a barrier structure This invention relates to contact structures for use in integrated circuits and methods of fabricating contact structures. In one embodiment, a contact structure includes a conductive layer, one or more barrier layers formed above the conductive layer, and a barrier... | 09/07/2004 |
| 6756678 | Conductive connection forming methods, oxidation reducing methods, and integrated circuits formed thereby A conductive connection forming method includes forming a first layer comprising a first metal on a substrate and forming a second layer comprising a second metal different from the first metal on the first layer. At least a part of the first layer may be transforme... | 06/29/2004 |
| 6747343 | Aluminum leadframes with two nickel layers A leadframe for use with integrated circuit chips comprising a leadframe base made of aluminum or aluminum alloy having a surface layer of zinc; a first layer of nickel on said zinc layer, said first nickel layer deposited to be compatible with aluminum and zinc; a ... | 06/08/2004 |
| 6703291 | Selective NiGe wet etch for transistors with Ge body and/or Ge source/drain extensions The wet etch stage of the salicide process normally used to fabricate polysilicon and silicon-based semiconductor transistors may not be appropriate for germanium-based transistors because the wet etch chemicals at such temperatures will dissolve the germ... | 03/09/2004 |
| 6690055 | Devices containing platinum-rhodium layers and methods A method of forming a rhodium-containing layer on a substrate, such as a semiconductor wafer, using complexes of the formula Ly RhYz is provided. Also provided is a chemical vapor co-deposited platinum-rhodium alloy barriers and elec... | 02/10/2004 |
| 6653737 | Interconnection structure and method for fabricating same An interconnection structure preferably including one or more conductors that have a central region filled with an insulator, and a method of fabricating such an interconnection structure for preferably making an electrical connection to the conductor(s).... | 11/25/2003 |
| 6639316 | Electrode having substrate and surface electrode components for a semiconductor device An electrode for a semiconductor device superior in die-bonding and wire-bonding characteristics with a submount and its manufacturing method are provided. The electrode is formed by ohmic-contacting the surface of a semiconductor, which comprises a subst... | 10/28/2003 |
| 6627964 | Gas sensor A gas sensor having a pn junction including two discrete electrical conductive-type layers, namely, a first semiconductor layer and a second semiconductor layer, disposed in contact with each other. Ohmic electrodes are formed on the respective surfaces o... | 09/30/2003 |
| 6624514 | Semiconductor device and manufacturing method thereof A semiconductor device includes a middle inter-level insulating film disposed on or above a semiconductor substrate, a conductive layer disposed on the middle inter-level insulating film, and an upper inter-level insulating film disposed on the middle int... | 09/23/2003 |
