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| Number | Title | Issue Date |
| 8154130 | Self-aligned metal to form contacts to Ge containing substrates and structure formed thereby A method for forming germano-silicide contacts atop a Ge-containing layer that is more resistant to etching than are conventional silicide contacts that are formed from a pure metal is provided. The method of the present invention includes first providing a structur... | 04/10/2012 |
| 8129844 | Method of forming a metal silicide layer, devices incorporating metal silicide layers and design structures for the devices Electronic devices and design structures of electronic devices containing metal silicide layers. The devices include: a thin silicide layer between two dielectric layers, at least one metal wire abutting a less than whole region of the silicide layer and in electric... | 03/06/2012 |
| 8072076 | Bond pad structures and integrated circuit chip having the same Bonding pad structures and integrated circuits having the same are provided. An exemplary embodiment of a bond pad structure comprises a bond pad layer. A passivation layer partially covers the bond pad layer from edges thereof and exposes a bonding surface, wherein... | 12/06/2011 |
| 8044514 | Semiconductor integrated circuit In a semiconductor integrated circuit, a second wiring layer includes a ground conductor having at least one opening formed therein. At least one opening is overlapped by at least one patch conductor included in a third wiring layer. At least one patch conductor and... | 10/25/2011 |
| 7915735 | Selective metal deposition over dielectric layers Selective deposition of metal over dielectric layers in a manner that minimizes or eliminates keyhole formation is provided. According to one embodiment, a dielectric target layer is formed over a substrate layer, wherein the target layer may be configured to allow ... | 03/29/2011 |
| 7649263 | Semiconductor device A semiconductor device including at least one conductive structure is provided. The conductive structure includes a silicon-containing conductive layer, a refractory metal salicide layer and a protection layer. The refractory metal salicide layer is disposed over th... | 01/19/2010 |
| 7449782 | Self-aligned metal to form contacts to Ge containing substrates and structure formed thereby A method for forming germano-silicide contacts atop a Ge-containing layer that is more resistant to etching than are conventional silicide contacts that are formed from a pure metal is provided. The method of the present invention includes first providing a structur... | 11/11/2008 |
| 7436067 | Methods for forming conductive structures and structures regarding same A method for forming a metal/metal oxide structure that includes forming metal oxide regions, e.g., ruthenium oxide regions, at grain boundaries of a metal layer, e.g., platinum. Preferably, the metal oxide regions are formed by diffusion of oxygen through grain bou... | 10/14/2008 |
| 7432202 | Method of substrate manufacture that decreases the package resistance A method includes forming a coating on a land contact of a package substrate, the coating including a first material disposed between a first layer and a second layer, each of the first layer and the second layer being made of a second material including gold. An ap... | 10/07/2008 |
| 7429781 | Memory package A memory chip package with a controller die on a first side of a printed circuit board and a memory die on a second side of the same printed circuit board. The memory chip package is integrated into a microprocessor controlled device or alternatively is integrated i... | 09/30/2008 |
| 7422707 | Highly conductive composition for wafer coating A conductive composition for coating a semiconductor wafer comprises conductive filler that has an average particle size of less than 2 microns and a maximum particle size of less than 10 microns, a first resin that has a softening point between 80-260° C., solvent... | 09/09/2008 |
| 7420227 | Cu-metalized compound semiconductor device The present invention is a compound semiconductor device characterized in that it is Cu-metalized to improved the reliability of the device and to greatly reduce the cost of production. ... | 09/02/2008 |
| 7420998 | Semiconductor laser device A semiconductor laser device has a front surface electrode formed by Au plating, a rear surface electrode formed by Au plating, an anti-adhesive film only on the front surface electrode and made of a material that does not react with Au, and a coating film that cove... | 09/02/2008 |
| 7414291 | Semiconductor device and method of manufacturing the same A method includes the steps of: implanting boron into a surface region of a silicon substrate to form a p+ diffused region; implanting indium into the surface of the p+ diffused region, to form an indium-implanted layer; forming a contact metal... | 08/19/2008 |
| 7399702 | Methods of forming silicide Methods of fully siliciding semiconductive materials of semiconductor devices are disclosed. A preferred embodiment comprises depositing an alloy comprised of a first metal and a second metal over a semiconductive material. The device is heated, causing atoms of the... | 07/15/2008 |
| 7385287 | Preventing damage to low-k materials during resist stripping A method of forming a feature in a low-k dielectric layer is provided. A low-k dielectric layer is placed over a substrate. A patterned photoresist mask is placed over the low-k dielectric layer. At least one feature is etched into the low-k dielectric layer. A CO c... | 06/10/2008 |
| 7371647 | Methods of forming transistors The invention encompasses a method of forming a structure over a semiconductor substrate. A silicon dioxide containing layer is formed across at least some of the substrate. Nitrogen is formed within the silicon dioxide containing layer. Substantially all of the nit... | 05/13/2008 |
| 7368665 | Circuit board and a power module employing the same A circuit board containing a metal-insulator composite member including an insulator substrate and a metal layer having a pattern, the composite member having an area where the spacing between a lower part of adjacent elements of the pattern on the metal layer which... | 05/06/2008 |
| 7368823 | Semiconductor device and method of manufacturing the same A method of manufacturing a semiconductor device having an interconnection part formed of multiple carbon nanotubes is disclosed. The method includes the steps of (a) forming a growth mode control layer controlling the growth mode of the carbon nanotubes, (b) formin... | 05/06/2008 |
| 7361027 | Contact structure, display device and electronic device A contact that takes a structure to laminate a protective conductive film over a metal film has a high hardness of the protective conductive film; therefore, a damage of contact surface made by contacting with an electrode of an inspection apparatus can be prevented... | 04/22/2008 |
| 7348265 | Semiconductor device having a silicided gate electrode and method of manufacture therefor The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the semiconductor device. The semiconductor device (100), among other possible elements, includes a gate oxide (140) located ov... | 03/25/2008 |
| 7332435 | Silicide structure for ultra-shallow junction for MOS devices A method of forming a semiconductor device comprising: forming a gate dielectric layer over a channel region; forming a gate electrode on the gate dielectric layer; forming source/drain regions substantially aligned with respective edges of the gate electrode with t... | 02/19/2008 |
| 7323783 | Electrode, method for producing same and semiconductor device using same There is provided a technology for obtaining an electrode having a low contact resistance and less surface roughness. There is provided an electrode comprising a semiconductor film 101, and a first metal layer 102 and a second metal layer 103 se... | 01/29/2008 |
| 7311946 | Methods for depositing metal films on diffusion barrier layers by CVD or ALD processes A process is described for depositing a metal film on a substrate surface having a diffusion barrier layer deposited thereupon. In one embodiment of the present invention, the process includes: providing a surface of the diffusion barrier layer that is substantially... | 12/25/2007 |
| 7309920 | Chip structure and process for forming the same A chip or wafer comprises a semiconductor substrate, first and second transistors on the semiconductor substrate, first and second metal layers over the semiconductor substrate, an insulating layer on the first and second metal layers, a third and fourth metal layer... | 12/18/2007 |
| 7303988 | Methods of manufacturing multi-level metal lines in semiconductor devices Methods of forming a multi-level metal line of a semiconductor device are disclosed. One example method includes subsequently stacking first and second metal layers, wherein a conductive etching stopper layer is interposed at an interface between the first and secon... | 12/04/2007 |
| 7291920 | Semiconductor structures In one aspect, the invention includes a method of forming a roughened layer of platinum, comprising: a) providing a substrate within a reaction chamber; b) flowing an oxidizing gas into the reaction chamber; c) flowing a platinum precursor into the reaction chamber ... | 11/06/2007 |
| 7285491 | Salicide process A salicide process is provided. A metal layer selected from a group consisting of nickel and an alloy thereof is formed on a silicon layer, the first step of the second thermal process is performed at 300˜400 degrees centigrade for 10˜60 seconds and the second ste... | 10/23/2007 |
| 7282408 | Surface treatment of an oxide layer to enhance adhesion of a ruthenium metal layer A method for forming a ruthenium metal layer on a dielectric layer comprises forming a silicon dioxide layer, then treating the silicon dioxide with a silicon-containing gas, for example silicon hydrides such as silane, disilane, or methylated silanes. Subsequently,... | 10/16/2007 |
| 7273808 | Reactive barrier/seed preclean process for damascene process A method for making a multilayer interconnect electronic component structure, and, in particular, an integrated circuit semiconductor device made using a copper damascene method is provided. The process of the invention uses a method for pre-cleaning exposed copper ... | 09/25/2007 |
| 7271486 | Retarding agglomeration of Ni monosilicide using Ni alloys A method for providing a low resistance non-agglomerated Ni monosilicide contact that is useful in semiconductor devices. Where the inventive method of fabricating a substantially non-agglomerated Ni alloy monosilicide comprises the steps of: forming a metal alloy l... | 09/18/2007 |
| 7271071 | Method of forming a catalytic surface comprising at least one of Pt, Pd, Co and Au in at least one of elemental and alloy forms The invention includes methods of forming a substrate having a surface comprising at least one of Pt, Pd, Co and Au in at least one of elemental and alloy forms. In one implementation, a substrate is provided which has a first substrate surface comprising at least o... | 09/18/2007 |
| 7256498 | Resistance-reduced semiconductor device and methods for fabricating the same Semiconductor devices and methods for fabricating the same. The semiconductor device includes a resistance-reduced transistor with metallized bilayer overlying source/drain regions and gate electrode thereof. A first dielectric layer with a conductive contact overli... | 08/14/2007 |
| 7250208 | Composite product with a thermally stressable bond between a fiber reinforced material and a further material In a material bond for a composite product composed of a fiber-reinforced material and a further material, such as an anode for an x-ray tube, wherein the fibers of the fiber-reinforced material exhibit a preferred orientation, and wherein the magnitude of the coeff... | 07/31/2007 |
| 7244996 | Structure of a field effect transistor having metallic silicide and manufacturing method thereof A field effect transistor having metallic silicide layers is formed in a semiconductor layer on an insulating layer of an SOI substrate. The metallic silicide layers are composed of refractory metal and silicon. The metallic silicide layers extend to bottom surfaces... | 07/17/2007 |
| 7235862 | Gate-enhanced junction varactor A semiconductor junction varactor utilizes gate enhancement for enabling the varactor to achieve a high ratio of maximum capacitance to minimum capacitance. ... | 06/26/2007 |
| 7230304 | Electric contacts and method of manufacturing thereof, and vacuum interrupter and vacuum circuit breaker using thereof An electric contact member which is excellent in voltage-proof performance and melt-resistant performance and excellent in mass productivity, and a method of manufacturing thereof, and a vacuum interrupter, a vacuum circuit breaker and a load-break switch for a road... | 06/12/2007 |
| 7220672 | Semiconductor device comprising metal silicide films formed to cover gate electrode and source-drain diffusion layers and method of manufacturing the same The invention provides a semiconductor device, and a manufacturing method, comprising a semiconductor substrate, a gate insulating film, a gate electrode, and a source-drain diffusion layer. A silicide film is formed on the gate electrode and the source-drain diffus... | 05/22/2007 |
| 7192888 | Low selectivity deposition methods A deposition method includes forming a nucleation layer over a substrate, forming a layer of a first substance at least one monolayer thick chemisorbed on the nucleation layer, and forming a layer of a second substance at least one monolayer thick chemisorbed on the... | 03/20/2007 |
| 7180109 | Field effect transistor and method of fabrication The present invention is a novel field effect transistor having a channel region formed from a narrow bandgap semiconductor film formed on an insulating substrate. A gate dielectric layer is formed on the narrow bandgap semiconductor film. A gate electrode is then f... | 02/20/2007 |
