Quotables
"This is the patent age of new inventions for killing bodies, and for saving souls. All propagated with the best intentions."
Lord Byron ;
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8080879 | Electrode structures for LEDs with increased active area An electrode structure is disclosed for enhancing the brightness and/or efficiency of an LED. The electrode structure can have a metal electrode and an optically transmissive thick dielectric material formed intermediate the electrode and a light emitting semiconduc... | 12/20/2011 |
| 8072075 | CuSiN/SiN diffusion barrier for copper in integrated-circuit devices The present invention relates to an integrated-circuit device that has at least one Copper-containing feature in a dielectric layer, and a diffusion-barrier layer stack arranged between the feature and the dielectric layer. The integrated-circuit device of the inven... | 12/06/2011 |
| 8056039 | Interconnect structure for integrated circuits having improved electromigration characteristics An interconnect structure for an integrated circuit (IC) device includes an elongated, electrically conductive line comprising one or more segments formed at a first width, w1, and one or more segments formed at one or more additional widths, w2 | 11/08/2011 |
| 7994640 | Nanoparticle cap layer Functionalized nanoparticles are deposited on metal lines inlaid in dielectric to form a metal cap layer that reduces electromigration in the metal line. The functionalized nanoparticles are deposited onto activated metal surfaces, then sintered and annealed to remo... | 08/09/2011 |
| 7977798 | Integrated circuit having a semiconductor substrate with a barrier layer An integrated circuit having a semiconductor substrate with a barrier layer is disclosed. The arrangement includes a semiconductor substrate and a metallic element. A carbon-based barrier layer is disposed between the semiconductor substrate and the metallic element... | 07/12/2011 |
| 7956469 | Light emitting device and method of manufacturing the same Provided is a light emitting device with high extraction efficiency, in which absorption of light by a conductive wire is prevented effectively. The light emitting device includes a conductive wire electrically connecting an electrode of a light emitting element and... | 06/07/2011 |
| 7777344 | Transitional interface between metal and dielectric in interconnect structures An integrated circuit structure and methods for forming the same are provided. The integrated circuit structure includes a semiconductor substrate; a dielectric layer over the semiconductor substrate; an opening in the dielectric layer; a conductive line in the open... | 08/17/2010 |
| 7709960 | Dual liner capping layer interconnect structure A high tensile stress capping layer on Cu interconnects in order to reduce Cu transport and atomic voiding at the Cu/dielectric interface. The high tensile dielectric film is formed by depositing multiple layers of a thin dielectric material, each layer being under ... | 05/04/2010 |
| 7667328 | Integration circuits for reducing electromigration effect An integrated circuit for reducing the electromigration effect. The IC includes a substrate and a power transistor which has first and second source/drain regions. The IC further includes first, second, and third electrically conductive line segments being (i) direc... | 02/23/2010 |
| 7586198 | Innerlayer panels and printed wiring boards with embedded fiducials Innerlayer panels are provided with high density fiducials during manufacture. The fiducials can be identified using X-rays without etching away portions of the innerlayer panel to expose the fiducials. ... | 09/08/2009 |
| 7547972 | Laminated structure, very-large-scale integrated circuit wiring board, and method of formation thereof The laminated structure includes a substrate of low dielectric constant material of silicon compound and an electroless copper plating layer laminated thereon with a barrier layer. The barrier layer is interposed between the substrate and the copper layer, and the b... | 06/16/2009 |
| 7436066 | Semiconductor element It is an object of the present invention to provide a highly reliable and high-quality semiconductor element by effectively preventing the migration of silver to a nitride semiconductor when an electrode main entirely or mostly of silver having high reflection effic... | 10/14/2008 |
| 7422977 | Copper adhesion improvement device and method A semiconductor device, in which a semiconductor integrated circuit having a multi-level interconnection structure is formed, according to an embodiment of the present invention, comprises a copper wiring and an insulating layer formed on a top surface of the copper... | 09/09/2008 |
| 7414275 | Multi-level interconnections for an integrated circuit chip Multilevel metallization layouts for an integrated circuit chip including transistors having first, second and third elements to which metallization layouts connect. The layouts minimize current limiting mechanism including electromigration by positioning the connec... | 08/19/2008 |
| 7397126 | Semiconductor device The present invention provides inhibiting an electrical leakage caused by anion migration. A trenched portion 15 is provided as ion migration-preventing zone between a source electrode 4 and a gate electrode 5. The trenched portion 15 is ... | 07/08/2008 |
| 7372160 | Barrier film deposition over metal for reduction in metal dishing after CMP A protective barrier layer, formed of a material such as titanium or titanium nitride for which removal by chemical mechanical polishing (CMP) is primarily mechanical rather than primarily chemical, formed on a conformal tungsten layer. During subsequent CMP to patt... | 05/13/2008 |
| 7348617 | Semiconductor device A semiconductor device comprising a ferroelectric capacitor having improved reliability is disclosed. According to one aspect of the present invention, it is provided a semiconductor device comprising a transistor formed on a semiconductor substrate, a ferroelectric... | 03/25/2008 |
| 7339267 | Semiconductor package and method for forming the same Semiconductor packages (100) that prevent the leaching of gold from back metal layers (118) into the solder (164) and methods for fabricating the same are provided. An exemplary method comprises providing a semiconductor wafer stack (110)... | 03/04/2008 |
| 7339270 | Semiconductor device and method for fabricating the same A semiconductor device has a porous low-dielectric-constant film formed on a substrate and having an opening and a fine particle film composed of a plurality of aggregately deposited fine particles each having a diameter of not less than 1 nm and not more than 2 nm ... | 03/04/2008 |
| 7339274 | Metallization performance in electronic devices Phenomena such as electromigration and stress-induced migration occurring in metal interconnects of devices such as integrated circuits are inhibited by use of underlying non-planarities. Thus the material underlying the interconnect is formed to have non-planaritie... | 03/04/2008 |
| 7339196 | Packaging of SMD light emitting diodes An SMD LED package with superior thermal dissipation capability is provided. The SMD LED package comprises a supporting block with circuit patterns and at least one LED attached to the supporting block. Wherein, circuit patterns of holes/vias, insulating layers, and... | 03/04/2008 |
| 7335995 | Microelectronic assembly having array including passive elements and interconnects A microelectronic assembly and a fabrication method are provided which includes a microelectronic element such as a chip or element of a package. A plurality of surface-mountable contacts are arranged in an array exposed at a major surface of the microelectronic ele... | 02/26/2008 |
| 7332814 | Bondwire utilized for coulomb counting and safety circuits A sense resistor and integrated circuit package combination is disclosed. A package lead frame is provided having a plurality of landing zones associated therewith and a die mounting area for mounting of a die thereon. The die has a plurality of bond pads associated... | 02/19/2008 |
| 7332812 | Memory card with connecting portions for connection to an adapter Semiconductor devices having conductive lines with extended ends and methods of extending conductive line ends by a variable distance are disclosed. An end of a first conductive feature of an interconnect structure is extended by a first distance, and an end of a se... | 02/19/2008 |
| 7329601 | Method of manufacturing semiconductor device Disclosed is a method for manufacturing a semiconductor device, comprising forming a low dielectric constant insulating film having a porous structure above a semiconductor substrate, forming a recess in the low dielectric constant insulating film, providing a buryi... | 02/12/2008 |
| 7327031 | Semiconductor device and method of manufacturing the same There is provided a solution to the problem of the poor adhesion in the pad portion while inhibiting the dishing in the pad portion. An SiON film, which covers insulating areas and has an opening above Cu pad areas, is formed, and a barrier metal film is formed in t... | 02/05/2008 |
| 7323781 | Semiconductor device and manufacturing method thereof The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon car... | 01/29/2008 |
| 7303985 | Zeolite-carbon doped oxide composite low k dielectric A method for forming a zeolite-carbon doped oxide (CDO) composite dielectric material is herein described. Zeolite particles may be dispersed in a solvent. The zeolite solvent solution may then be deposited on an underlying layer, such as a wafer of other dielectric... | 12/04/2007 |
| 7303988 | Methods of manufacturing multi-level metal lines in semiconductor devices Methods of forming a multi-level metal line of a semiconductor device are disclosed. One example method includes subsequently stacking first and second metal layers, wherein a conductive etching stopper layer is interposed at an interface between the first and secon... | 12/04/2007 |
| 7301241 | Semiconductor device for preventing defective filling of interconnection and cracking of insulating film The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 | 11/27/2007 |
| 7301239 | Wiring structure to minimize stress induced void formation A wiring structure with improved resistance to void formation and a method of making the same are described. The wiring structure has a first conducting layer that includes a large area portion which is connected to an end of a protrusion with a plurality of “n”... | 11/27/2007 |
| 7298021 | Electronic device and method for manufacturing the same An electronic device is provided using wiring comprising aluminum to prevent hillock or whisker from generating, wherein the wiring contains oxygen atoms at a concentration of 8×1018 atoms·cm−3 or less, carbon atoms at a concentration of 5... | 11/20/2007 |
| 7291558 | Copper interconnect wiring and method of forming thereof Capping layer or layers on a surface of a copper interconnect wiring layer for use in interconnect structures for integrated circuits and methods of forming improved integration interconnection structures for integrated circuits by the application of gas-cluster ion... | 11/06/2007 |
| 7285860 | Method and structure for defect monitoring of semiconductor devices using power bus wiring grids A method for implementing defect inspection of an integrated circuit includes configuring a power bus grid structure on a first metal interconnect level, the power bus grid structure including a first plurality of wire pairs. The first plurality of wire pairs is arr... | 10/23/2007 |
| 7276796 | Formation of oxidation-resistant seed layer for interconnect applications An interconnect structure of the single or dual damascene type and a method of forming the same, which substantially reduces the surface oxidation problem of plating a conductive material onto a noble metal seed layer are provided. In accordance with the present inv... | 10/02/2007 |
| 7272028 | MRAM cell with split conductive lines A magnetoresistive memory cell includes N magnetoresistive elements conductively connected in series (where N is an integer greater than or equal to two). The magnetoresistive elements, respectively, are positioned between at least two adjacent conductive lines. At ... | 09/18/2007 |
| 7271097 | Method for manufacturing a semiconductor protection element and a semiconductor device A semiconductor protection element is provided in which no heat generation occurs in a concentrated manner, in a region having a high resistance value even when electrostatic discharge (ESD) is applied, without an increase in an area of the semiconductor device. The... | 09/18/2007 |
| 7271403 | Isolating phase change memory devices A phase change memory may be made using an isolation diode in the form of a Schottky diode between a memory cell and a word line. The use of Schottky diode isolation devices may make the memory more scaleable in some embodiments. ... | 09/18/2007 |
| 7271700 | Thin film resistor with current density enhancing layer (CDEL) A thin film resistor device and method of manufacture includes a layer of a thin film conductor material and a current density enhancing layer (CDEL). The CDEL is an insulator material adapted to adhere to the thin film conductor material and enables the said thin f... | 09/18/2007 |
| 7265447 | Interconnect with composite layers and method for fabricating the same Composite ALD-formed diffusion barrier layers. In a preferred embodiment, a composite conductive layer is composed of a diffusion barrier layer and/or a low-resistivity metal layer formed by atomic layer deposition (ALD) lining a damascene opening in dielectrics, se... | 09/04/2007 |
