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Pet Toilet-Like Water Disk and Food Storage
One pet-friendly inventor patented "a device for watering pets, e.g., a dog or cat." The device, he helpfully noted, "has the general shape of a toilet."
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| Number | Title | Issue Date |
| 8067831 | Integrated circuit package system with planar interconnects An integrated circuit package system is provided including forming a first substrate, mounting a first integrated circuit to the first substrate, and forming first planar interconnects in contact with the first integrated circuit and electrically connecting the firs... | 11/29/2011 |
| 7459780 | Fan-out wire structure This invention discloses a fan-out wire structure for use in a display panel of a display device. The fan-out wire structure comprises a first metal layer, a first insulation layer, and a second metal layer. The first insulation layer is formed on the first metal la... | 12/02/2008 |
| 7420271 | Heat conductivity and brightness enhancing structure for light-emitting diode A heat conductivity and brightness enhancing structure for light-emitting diode, including a bracket having a cathode leg support. A bowl structure is formed on upper end of the cathode leg support for resting a light-emitting chip therein. At least one depression i... | 09/02/2008 |
| 7378727 | Memory device and a method of forming a memory device A memory device includes a semiconductor substrate having a surface, a plurality of first and second conductive lines, a plurality of memory cells, and a plurality of landing pads. Each of the first conductive lines has a line width wb and two neighboring ones of th... | 05/27/2008 |
| 7361533 | Stacked embedded leadframe A method of forming a stackable embedded leadframe package includes coupling an electronic component having bond pads to a substrate; coupling on the substrate a leadframe having a plurality of leads, each lead having a lower mounting portion; encapsulating the elec... | 04/22/2008 |
| 7348494 | Signal layer interconnects Inner layer traces on a multilayer printed wiring board are exposed to enable direct interconnection with another device such as a printed wiring board. The traces may be exposed by removing at least some of the dielectric substrate material around the traces, or by... | 03/25/2008 |
| 7329946 | I/O architecture for integrated circuit package A circuit package may include an upper surface of first conductive elements and second conductive elements. The first conductive elements may receive input/output signals from respective conductive elements of an integrated circuit die, and the second conductive ele... | 02/12/2008 |
| 7323776 | Elevated heat dissipating device The elevated heat dissipating device of the present invention comprises a thermal substrate connecting onto a heat source and at least one heat conductive pipe connecting to the thermal substrate. The heat conductive pipe further comprises a connecting part connecte... | 01/29/2008 |
| 7315080 | Ball grid array package that includes a collapsible spacer for separating die adapter from a heat spreader A ball grid array package is manufactured by mounting a semiconductor die to a first surface of a substrate and mounting a die adapter to the semiconductor die. The semiconductor die is wire bonded to ones of conductive traces of the substrate. A collapsible spacer ... | 01/01/2008 |
| 7239008 | Semiconductor apparatus and method for fabricating the same A semiconductor apparatus includes a semiconductor pellet having electrodes thereon; a plurality of lead terminals, which electrically connect the electrodes of the semiconductor pellet to terminals formed on a substrate; and a molding member, which is filled around... | 07/03/2007 |
| 7224054 | Semiconductor device and system having semiconductor device mounted thereon A ball grid array packaged semiconductor device mounted on a mounting board and including pads formed within a package and are connected to signal lines of a bare chip by bonding wires. There are formed first vias extending from the respective pads to a bottom surfa... | 05/29/2007 |
| 7192807 | Wafer level package and fabrication method A method of forming an electronic component package includes coupling a first surface of an electronic component to a first surface of a first dielectric strip, the electronic component comprising bond pads on the first surface; forming first via apertures through t... | 03/20/2007 |
| 7115977 | Multi-chip package type semiconductor device A multi-chip package type semiconductor device includes an insulating substrate having first and second conductive patterns thereon, a first semiconductor chip on the insulating substrate and having a first terminal pad and a relay pad isolated from the first termin... | 10/03/2006 |
| 7109573 | Thermally enhanced component substrate An IC package dissipates thermal energy using thermally and electrically conductive projections. The IC package includes a substrate material with a die pad area, which is suitable to support an integrated circuit. A plurality of solder ball pads is disposed on a fi... | 09/19/2006 |
| 7102211 | Semiconductor device and hybrid integrated circuit device The related arts have difficulty in efficiently dissipating the heat generated by a resin-molded semiconductor element, and thus have the problem of thermal stress causing damage to the semiconductor element. To solve the problem, a semiconductor device of the prefe... | 09/05/2006 |
| 7095100 | Semiconductor device and method of making the same A semiconductor device and a method of making a semiconductor device are provided, wherein the device includes a die-pad, a semiconductor chip and a sealing resin. The die-pad has a first surface and a second surface opposite to the first surface. The second surface... | 08/22/2006 |
| 7091581 | Integrated circuit package and process for fabricating the same A process for fabricating an integrated circuit package includes: selectively etching a leadframe strip to define a die attach pad and at least one row of contact pads; mounting a semiconductor die to one side of the leadframe strip, on the die attach pad; wire bond... | 08/15/2006 |
| 7084474 | Photosensitive semiconductor package and method for fabricating the same A photosensitive semiconductor package and a method for fabricating the same are proposed. The package includes a carrier having a first surface, an opposite second surface, and an opening penetrating the carrier; a photosensitive chip having an active surface and a... | 08/01/2006 |
| 7053627 | Impedance standard substrate and method for calibrating vector network analyzer An impedance standard substrate for calibrating a vector network analyzer comprises a first surface and a second surface opposite to the first surface. A thru-circuit has two contacts electrically connected to each other. The two contacts are disposed on the first s... | 05/30/2006 |
| 7049166 | Methods and apparatus for making integrated circuit package including opening exposing portion of the IC A method for making an IC package preferably includes providing a mold including first and second mold portions, and wherein the first mold portion carries a mold protrusion defining an IC-contact surface with peripheral edges and a bleed-through retention channel p... | 05/23/2006 |
| 7038315 | Semiconductor chip package A semiconductor chip package that includes discrete conductive leads in electrical contact with bond pads on a semiconductor chip. This chip/lead assembly is encapsulated within an encapsulating material and electrode bumps are formed through the encapsulating mater... | 05/02/2006 |
| 7012325 | Ultra-thin semiconductor package device and method for manufacturing the same An ultra-thin semiconductor package includes a lead frame having a die pad and a plurality of leads surrounding the die pad. The die pad includes a chip attaching part to which a semiconductor chip is attached and a peripheral part integral with and surrounding the ... | 03/14/2006 |
| 7009286 | Thin leadless plastic chip carrier A leadless plastic chip carrier is fabricated by selectively etching a leadframe strip to reduce a thickness of the strip at a portion thereof. Selectively masking the surface of the leadframe strip using a mask, follows selectively etching, to provide exposed areas... | 03/07/2006 |
| 6992372 | Film carrier tape for mounting electronic devices thereon The present invention provides a flat film carrier tape for mounting electronic devices thereon which tape can enhance reliability of a semiconductor chip mounting line. The film carrier tape includes a continuous insulating layer, a wiring pattern formed of a condu... | 01/31/2006 |
| 6984884 | Electric power semiconductor device A main lead (2) is a single body comprised of an inner lead (2a) and an outer lead (2b) which are integrally formed, the bonding wires are arranged in parallel and fixed onto the inner lead (2a) by the wire bonding po... | 01/10/2006 |
| 6975020 | Semiconductor integrated circuit having pads layout for increasing signal integrity and reducing chip size A semiconductor integrated circuit device includes a semiconductor chip having a memory cell array region surrounded with a peripheral circuit region and includes a plurality of bonding pads disposed at least in one row on only one side of the semiconductor chip. Th... | 12/13/2005 |
| 6964918 | Electronic components such as thin array plastic packages and process for fabricating same A process for fabricating an integrated circuit package includes establishing a plating mask on a first surface of a metal carrier. The plating mask defines a plurality of components including a die attach pad, at least one row of contact pads and at least one addit... | 11/15/2005 |
| 6965154 | Semiconductor device A semiconductor device and a manufacturing method thereof are provided with downsizing and densification achieved by reducing the thickness of the semiconductor device without increase in area. Terminal electrodes are arranged, in plan view, outside a region where s... | 11/15/2005 |
| 6946726 | Chip carrier substrate with a land grid array and external bond terminals A carrier for a semiconductor die has a substrate with a cavity formed in the substrate. The cavity has a bottom and sidewalls, and the sidewalls have a stepped tier. Electrically conductive contacts are disposed on an underside of the substrate. Electrically conduc... | 09/20/2005 |
| 6920051 | Hybrid capacitor, circuit, and system A hybrid capacitor associated with an integrated circuit package provides multiple levels of excess, off-chip capacitance to die loads. The hybrid capacitor includes a low inductance, parallel plate capacitor embedded within the package, and electrically connected t... | 07/19/2005 |
| 6916683 | Methods of fabricating a molded ball grid array A method and apparatus for encapsulating a BGA package. Specifically, a BGA package is encapsulated after the balls are attached to the package. The backside of the package having the balls disposed thereon may be completely covered by the encapsulant. The encapsula... | 07/12/2005 |
| 6897556 | I/O architecture for integrated circuit package A circuit package may include an upper surface of first conductive elements and second conductive elements. The first conductive elements may receive input/output signals from respective conductive elements of an integrated circuit die, and the second conductive ele... | 05/24/2005 |
| 6885051 | Minimally spaced MRAM structures A method of forming minimally spaced apart MRAM structures is disclosed. A photolithography technique is employed to define patterns an integrated circuit, the width of which is further reduced by etching to allow formation of patterns used to etch digit line region... | 04/26/2005 |
| 6861750 | Ball grid array package with multiple interposers Electrically, thermally and mechanically enhanced ball grid array (BGA) packages are described. An IC die is mounted to a first surface of a first stiffener. A peripheral edge portion of a second surface of the first stiffener is attached to a first surface of a sec... | 03/01/2005 |
| 6833612 | Flip-chip image sensor packages The present invention provides flip-chip packaging for optically interactive devices such as image sensors and methods of assembly. In a first embodiment of the invention, conductive traces are formed directly on the second surface of a transparent substrate and an ... | 12/21/2004 |
| 6794741 | Three-dimensional stacked semiconductor package with pillars in pillar cavities A three-dimensional stacked semiconductor package includes first and second semiconductor chip assemblies and a conductive bond. The first semiconductor chip assembly includes a first semiconductor chip and a first conductive trace with a first routing line and a fi... | 09/21/2004 |
| 6774479 | Electronic device having a semiconductor chip on a semiconductor chip connection plate and a method for producing the electronic device The invention relates to an electronic device having a semiconductor chip and a leadframe. The leadframe has a flat conductor frame. A semiconductor chip connection plate is configured in the center of the flat conductor frame. The semiconductor chip connection plat... | 08/10/2004 |
| 6747344 | Lead frame assemblies with voltage reference plane and IC packages including same A semiconductor die assembly employing a voltage reference plane structure electrically isolated from, but in immediate proximity to, leads of a lead frame to which the die is electrically connected. A non-conductive adhesive or an adhesively-coated dielectric film ... | 06/08/2004 |
| 6744123 | Film carrier tape for mounting electronic devices thereon and method of manufacturing the same The invention provides a film carrier tape for mounting electronic devices thereon, which film carrier tape enables reliable formation of a predetermined wiring pattern in a pattern-forming region and lower production cost. The film carrier tape of the present inven... | 06/01/2004 |
| 6737736 | Semiconductor device A semiconductor device and a manufacturing method for downsizing and densification achieved by reducing the thickness of the semiconductor device without an increase in area. Terminal electrodes are arranged, in plan view, outside a region where semiconductor chips ... | 05/18/2004 |
