Did You Know...
...that in the early 1940s GE engineer James Wright was charged with a task of utmost importance to the war effort: develop a cheap substitute for rubber that could be used to produce tires, gas masks and a whole host of military gear. Wright tackled the task diligently -- and wound up inventing Silly Putty.
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| Number | Title | Issue Date |
| 8183684 | Semiconductor device and method of manufacturing the same Provided is a thin semiconductor device using a thin metal wire and having a low top portion. The semiconductor device of the present invention has a structure in which a bonding pad 55 of a semiconductor chip 54 and an electrode 53B are connect... | 05/22/2012 |
| 8174111 | Vertical mount package for MEMS sensors A vertical mount pre-molded type package for use with a MEMS sensor may be formed with a low moisture permeable molding material that surrounds a portion of the leadframes and forms a cavity in which one or multiple dies may be held. The package includes structures ... | 05/08/2012 |
| 8174110 | Semiconductor device having at least two terminals among the plurality of terminals electrically connected to each other while not being adjacent to one other and not being connected to internal circuit A semiconductor device includes a base substrate including an internal circuit, a resin protrusion part that is disposed to protrude on an active face side of the base substrate, and a plurality of terminals that are formed by including an island-shaped conductive f... | 05/08/2012 |
| 8169070 | Semiconductor device The semiconductor device comprises a semiconductor chip defining a first face and a second face opposite to the first face, the semiconductor chip comprising at least one contact element on the first face of the semiconductor chip, an encapsulating body encapsulatin... | 05/01/2012 |
| 8148809 | Semiconductor device, method for manufacturing the same, and multilayer substrate having the same A method for manufacturing a semiconductor device includes: preparing a wafer formed of a SOI substrate; forming a circuit portion in a principal surface portion; removing a support substrate of the SOI substrate; fixing an insulation member on a backside of a semic... | 04/03/2012 |
| 8138595 | Integrated circuit packaging system with an intermediate pad and method of manufacture thereof A method of manufacture of an integrated circuit packaging system includes: forming an elevated contact above and between a lead and a die pad that is coplanar with the lead; connecting an integrated circuit and the lead; attaching a jumper interconnect between the ... | 03/20/2012 |
| 8120164 | Semiconductor chip package, printed circuit board assembly including the same and manufacturing methods thereof A semiconductor chip package and printed circuit board assembly including the same which have a variable mounting orientation include a semiconductor chip disposed on a first surface of an insulating substrate, connectors symmetrically disposed at respective first a... | 02/21/2012 |
| 8115297 | Substrate structure with die embedded inside and dual build-up layers over both side surfaces and method of the same The present invention comprises a first substrate with a die formed on a die metal pad, a first and a second wiring circuits formed on the surfaces of the first substrate. A second substrate has a die opening window for receiving the die, a third wiring circuit is f... | 02/14/2012 |
| 8115296 | Electronic device package Various embodiments for molding tools for moisture-resistant image sensor packaging structures and methods of assembly are disclosed. Image sensor packages of the present invention include an interposer, a housing structure formed on the interposer for surrounding a... | 02/14/2012 |
| 8115298 | Semiconductor device A semiconductor device is disclosed which includes a tab (5) for use in supporting a semiconductor chip (8), a seal section (12) as formed by sealing the semiconductor chip (8) with a resin material, more than one tab suspension lead (... | 02/14/2012 |
| 8110913 | Integrated circuit package system with integral inner lead and paddle An integrated circuit package system includes: fabricating a lead frame including: providing inner leads having an inner lead pitch of progressive length, forming a lead shoulder, on the inner leads, having a shoulder height of a progressive height, and forming oute... | 02/07/2012 |
| 8110914 | Wafer level package with removable chip protecting layer A wafer level package includes a chip, a removable resin layer, a molding material, a dielectric layer, redistribution lines and a solder resist. The removable resin layer is formed to surround side surfaces and a lower surface of the chip. The molding material is f... | 02/07/2012 |
| 8110915 | Open cavity leadless surface mountable package for high power RF applications An RF semiconductor package includes a substrate having generally planar top and bottom surfaces. The substrate includes a metallic base region and one or more metallic signal terminal regions extending from the top surface to the bottom surface, and an insulative m... | 02/07/2012 |
| 8106504 | Stacking package structure with chip embedded inside and die having through silicon via and method of the same The semiconductor device package structure includes a first die with a through silicon via (TSV) open from back side of the first die to expose bonding pads; a build up layer coupled between the bonding pads to terminal metal pads by the through silicon via (TSV); a... | 01/31/2012 |
| 8097944 | Semiconductor device A semiconductor device includes a substrate having a chip island, a chip attached to the chip island, and encapsulation material deposited on the chip and part of the chip island. The chip island includes a first main face to which the chip is attached opposite a se... | 01/17/2012 |
| 8084853 | Semiconductor flip chip package utilizing wire bonding for net switching This invention provides a semiconductor flip chip package including a carrier substrate and a flip chip mounted on the carrier substrate. The flip chip comprises a first input/output (I/O) pad and a second I/O pad on an active surface of the flip chip, wherein a swi... | 12/27/2011 |
| 8058721 | Package structure Disclosed is a package structure including a semiconductor chip disposed in a core board having a first surface and an opposite second surface. The package structure further includes a plurality of first and second electrode pads disposed on an active surface and an... | 11/15/2011 |
| 8049324 | Preventing access to stub traces on an integrated circuit package An integrated circuit (IC) package includes a printed circuit board (PCB) substrate and a plurality of package attachment terminals. The package attachment terminals are used to conduct electrical signals from a die that is attached and bonded onto the PCB substrate... | 11/01/2011 |
| 8049325 | Integrated circuit devices having printed circuit boards therein with staggered bond fingers that support improved electrical isolation An integrated circuit substrate includes an integrated circuit chip having a plurality of electrically conductive pads on a surface thereof and a printed circuit board mounted to the integrated circuit chip. The printed circuit board includes an alternating arrangem... | 11/01/2011 |
| 8044502 | Composite contact for fine pitch electrical interconnect assembly An electrical interconnect assembly for electrically interconnecting terminals on a first circuit member with terminals on a second circuit member. The electrical interconnect includes a housing having a plurality of through openings extending between a first surfac... | 10/25/2011 |
| 8044501 | Contact structure, display device and electronic device A contact that takes a structure to laminate a protective conductive film over a metal film has a high hardness of the protective conductive film; therefore, a damage of contact surface made by contacting with an electrode of an inspection apparatus can be prevented... | 10/25/2011 |
| 8039947 | Integrated circuit package system with different mold locking features An integrated circuit package system is provided including forming a first inner lead having a first inner bottom side and a first outer lead, forming a first side lock of the first inner lead above the first inner bottom side, connecting an integrated circuit die w... | 10/18/2011 |
| 8035213 | Chip package structure and method of manufacturing the same A chip package structure and a method of manufacturing the same are provided. The chip package structure includes a package portion and a plurality of external conductors. The package portion includes a distribution layer, a chip, a plurality internal conductors and... | 10/11/2011 |
| 8026591 | Semiconductor device with lead terminals having portions thereof extending obliquely A semiconductor device in which a semiconductor chip, a lead frame and metal wires for electrically connecting the lead frame are sealed with sealing resin. The lead frame has a plurality of lead terminal portions, a supporting portion for supporting the semiconduct... | 09/27/2011 |
| 7994632 | Interdigitated conductive lead frame or laminate lead frame for GaN die A GaN die having a plurality of parallel alternating and closely spaced source and drain strips is contacted by parallel coplanar comb-shaped fingers of source and drain pads. A plurality of enlarged area coplanar spaced gate pads having respective fingers contactin... | 08/09/2011 |
| 7989945 | Spring connector for making electrical contact at semiconductor scales A connector for electrically connecting to pads formed on a semiconductor device includes a substrate and an array of contact elements of conductive material formed on the substrate. Each contact element includes a base portion attached to the top surface of the sub... | 08/02/2011 |
| 7982304 | Chip package structure A chip package structure including a substrate, at least one chip, a heat dissipation device, at least one first conductive bar, a molding compound, and at least one second conductive bar is provided. The chip and the heat dissipation device are respectively dispose... | 07/19/2011 |
| 7977783 | Wafer level chip size package having redistribution layers A wafer level chip size package (WLCSP) and a method of manufacturing the same are disclosed. Lands are formed at the ends of redistribution layers. The redistribution layers excluding the lands and a first dielectric layer are covered with a second dielectric layer... | 07/12/2011 |
| 7977782 | Integrated circuit package system with dual connectivity An integrated circuit package system includes: forming a lead having a both top contact portion and a bottom contact portion; connecting an integrated circuit die and the lead; and forming a package encapsulation, having a top side and a bottom side, over the integr... | 07/12/2011 |
| 7968997 | Semiconductor device A semiconductor device includes a wring board having a first surface with external connection terminals and a second surface with internal connection terminals. On the second surface of the wiring board, a semiconductor chip having electrode pads is mounted. The ele... | 06/28/2011 |
| 7960825 | Chip package and method for fabricating the same A method for fabricating chip package includes providing a semiconductor chip with a bonding pad, comprising an adhesion/barrier layer, connected to a pad through an opening in a passivation layer, next adhering the semiconductor chip to a substrate using a glue mat... | 06/14/2011 |
| 7956453 | Semiconductor package with patterning layer and method of making same In accordance with the present invention, there is provided multiple embodiments of a semiconductor package including one or more semiconductor dies which are electrically connected to an underlying substrate through the use of a conductive pattern which is at least... | 06/07/2011 |
| 7952186 | Semiconductor package land grid array substrate and plurality of first and second electrodes A semiconductor package includes a bare chip which has a plurality of external electrodes, a land grid array substrate having an edge, a first surface and a second surface. The first surface includes a first portion apart from the edge and a second portion adjacent ... | 05/31/2011 |
| 7928555 | Stack semiconductor package including an interposer chip having an imposed diode or capacitor A stacked semiconductor package may include a wiring substrate. A first semiconductor chip may be disposed on the wiring substrate and wire-bonded to the wiring substrate. An interposer chip may be disposed on the wiring substrate and sire bonded to the wiring subst... | 04/19/2011 |
| 7928554 | IC chip, antenna, and manufacturing method of the IC chip and the antenna An antenna used for an ID chip or the like is disclosed with planarized antenna unevenness and an IC chip having such the antenna with a flat surface is disclosed. Manufacturing an integrated circuit mounted with an antenna is facilitated. A laminated body formed by... | 04/19/2011 |
| 7923831 | LED-based light source having improved thermal dissipation A light source having a plurality of dies mounted on leads that are partially enclosed in a plastic body is disclosed. Each die is powered by first and second contacts. One contact is connected to the lead on which the die is mounted. Light from the LED exits the di... | 04/12/2011 |
| 7902657 | Self locking and aligning clip structure for semiconductor die package A semiconductor die package. The semiconductor die package includes a semiconductor die, and a lead comprising a flat surface. It also includes a clip structure including a (i) a contact portion, where the contact portion is coupled the semiconductor die, a clip ali... | 03/08/2011 |
| 7902658 | Integrated circuit having wide power lines A semiconductor integrated circuit device described herein includes a semiconductor chip and a package on which the semiconductor chip is disposed. The semiconductor chip includes first electrode pads, and the package includes second electrode pads connected to the ... | 03/08/2011 |
| 7880287 | Stud bumps for die alignment Embodiments include but are not limited to apparatuses and systems including a package having stud bumps for die alignment. A package may include a package substrate, and a plurality of stud bumps coupled to the package substrate. The stud bumps may define a die reg... | 02/01/2011 |
| 7875968 | Leadframe, semiconductor package and support lead for bonding with groundwires Leadframe for a semiconductor package and manufacturing from such leadframe including a plurality of connection leads supported in a frame. Die mounting plate is centrally located in the leadframe and is supported by a plurality of support leads which are electrical... | 01/25/2011 |
