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| Number | Title | Issue Date |
| 8178963 | Wafer level package with die receiving through-hole and method of the same The present invention discloses a structure of package comprising: a substrate with a die receiving through hole, a connecting through hole structure and a first contact pad; a die disposed within the die receiving through hole; a surrounding material formed under t... | 05/15/2012 |
| 8169069 | Integrated semiconductor outline package A transistor outline package is provided for a semiconductor integrated device suitable for use in a control module of an automobile for connection between a printed circuit board and a bus bar of such a module. The package includes a package housing, having a first... | 05/01/2012 |
| 8143714 | Integrated circuit and method for producing the same An integrated circuit provides a carrier substrate, a wiring level above a carrier substrate, wherein the wiring level comprises a first conductor track composed of a first conductive material and a second conductor track composed of the first conductive material, a... | 03/27/2012 |
| 8129837 | Flip chip interconnection pad layout A flip chip interconnect pad layout has the die signal pads are arranged on the die surface near the perimeter of the die, and the die power and ground pads arranged on the die surface inboard from the signal pads; and has the signal pads on the corresponding packag... | 03/06/2012 |
| 8129836 | Semiconductor device A semiconductor device is composed of a pair of semiconductor chips (402, 404) arranged parallel on the same flat plane; a high voltage bus bar (21) bonded on the surface on the collector side of one semiconductor chip (402); a low voltage bus b... | 03/06/2012 |
| 8115295 | Semiconductor device A miniaturized semiconductor device has a package substrate, a semiconductor chip mounted on the main surface of the package substrate and having plural LNAs each for amplifying a signal, an RF VCO for converting the frequency of the signal supplied from each LNA, a... | 02/14/2012 |
| 8106503 | High frequency semiconductor device According to one embodiment, a high frequency semiconductor device is provided, which includes: a distribution/input matching circuit board that mounts thereon a distribution/input matching circuit and an input transmission line pattern; an input capacitor board tha... | 01/31/2012 |
| 8097943 | Semiconductor device and method of forming wafer level ground plane and power ring A semiconductor die has active circuits formed on its active surface. Contact pads are formed on the active surface of the semiconductor die and coupled to the active circuits. A die extension region is formed around a periphery of the semiconductor die. Conductive ... | 01/17/2012 |
| 8097942 | Semiconductor device including power supply bar having jutted portion, parallel running portion and bent portion and manufacturing method therefor A semiconductor device and a manufacturing method therefor wherein a wire for coupling an inner lead and a semiconductor chip with each other can be prevented from being electrically short-circuited to any other conductive part are provided. An inner lead portion ha... | 01/17/2012 |
| 8093707 | Leadframe packages having enhanced ground-bond reliability Various semiconductor package arrangements and methods that improve the reliability of wire bonding a die to ground or other outside contacts are described. In one aspect, selected ground pads on the die are wire bonded to a bonding region located on the tie bar por... | 01/10/2012 |
| 8084852 | Hybrid integrated circuit device, and method for fabricating the same, and electronic device A hybrid integrated circuit device having high mount reliability comprises a module substrate which is a ceramic wiring substrate, a plurality of electronic component parts laid out on the main surface of the module substrate, a plurality of electrode terminals laid... | 12/27/2011 |
| 8072058 | Semiconductor package having a plurality input/output members A semiconductor package has a first substrate having a plurality of electrically conductive patterns formed thereon. A first semiconductor die is coupled to the plurality of conductive patterns. A second semiconductor die is coupled to the first semiconductor die by... | 12/06/2011 |
| 8063480 | Printed board and semiconductor integrated circuit An IC which includes a first circuit and a plurality of first paired terminals each including a first power supply terminal and a first GND terminal which are connected to the first circuit, and a second circuit and a plurality of second paired terminals each includ... | 11/22/2011 |
| 8058720 | Semiconductor package A semiconductor package includes a die pad; a semiconductor die mounted on the die pad; a plurality of leads in a first horizontal plane disposed along peripheral edges of the die pad; a ground bar downset from the first horizontal plane to a second horizontal plane... | 11/15/2011 |
| 8044500 | Power module substrate, method for manufacturing power module substrate, and power module Disclosed is a power module having improved joint reliability. Specifically disclosed is a power module including a power module substrate wherein a circuit layer is brazed on the front surface of a ceramic substrate, a metal layer is brazed on the rear surface of t... | 10/25/2011 |
| 8039946 | Chip package structure and fabricating method thereof A chip package structure including a chip, a lead frame, first bonding wires and second bonding wires is provided. The chip has an active surface and chip bonding pads disposed thereon. The lead frame is fixed on the chip and the lead frame includes inner leads, at ... | 10/18/2011 |
| RE42776 | Tap connections for circuits with leakage suppression capability An integrated circuit biases the substrate and well using voltages other than those used for power and ground. Tap cells inside the standard cell circuits are removed. New tap cells used to bias the substrate and well reside outside the standard cell circuits. The l... | 10/04/2011 |
| 7994631 | Substrate for an integrated circuit package and a method of forming a substrate A substrate for an integrated circuit package is disclosed. The substrate comprises a core comprising a first dielectric layer having a first thickness; conductive traces formed on the first dielectric layer for routing signals within the integrated circuit package,... | 08/09/2011 |
| 7994630 | Power transistor package with integrated bus bar According to one embodiment, a power transistor package includes an electrically conductive flange configured to be connected to a source of a power transistor device. The package further includes a first terminal mechanically fastened to the flange and configured t... | 08/09/2011 |
| 7986037 | Low noise semiconductor device As a power feed route in a semiconductor chip, a power feed route which reduces antiresonance impedance in the frequency range of tens of MHz is to be realized thereby to suppress power noise in a semiconductor device. By inserting structures which raise the resista... | 07/26/2011 |
| 7986036 | Power/ground network of integrated circuits and arrangement thereof An arrangement scheme for a power/ground (P/G) network of an integrated circuit is provided. Rows of standard cells in the integrated circuit are horizontally arranged. The P/G network has horizontal and vertical metal lines arranged in different metal layers. The h... | 07/26/2011 |
| 7982301 | Semiconductor device A miniaturized semiconductor device has a package substrate, a semiconductor chip mounted on the main surface of the package substrate and having plural LNAs each for amplifying a signal, an RF VCO for converting the frequency of the signal supplied from each LNA, a... | 07/19/2011 |
| 7982303 | Semiconductor device and communication method A semiconductor chip is disposed on a first surface of a mounting board with its active surface upward. An inductor is provided at the active surface side, that is, at the surface side of the semiconductor chip not facing the mounting board in order to perform commu... | 07/19/2011 |
| 7982302 | Power semiconductor module with control functionality and integrated transformer A power semiconductor module comprising: a substrate, a plurality of conductor tracks arranged thereon, the conductor tracks being electrically insulated from one another, and including power semiconductor components arranged thereon; a connecting device, composed o... | 07/19/2011 |
| 7960824 | Semiconductor device including power supply pad and trunk wiring which are arranged at the same layer level A semiconductor device includes a semiconductor substrate which includes a functional circuit, a trunk wiring which passes through a portion near a position immediately above a center portion of the functional circuit, a power supply pad which is connected to an end... | 06/14/2011 |
| 7960823 | Semiconductor device with different sized ESD protection elements A semiconductor device of an aspect of the present invention comprises a package substrate, one first power supply terminal provided on the package substrate, one second power supply terminal provided on the package substrate, a semiconductor chip disposed on the pa... | 06/14/2011 |
| 7944041 | Integrated semiconductor substrate structure using incompatible processes A plurality of FPGA dice is disposed upon a semiconductor substrate. In order both to connect thousands of signal interconnect lines between the plurality of FPGA dice and to supply the immense power required, it is desired that the substrate construction include tw... | 05/17/2011 |
| 7936060 | Reworkable electronic device assembly and method An electronic device assembly is provided which includes a substrate, an interposer and an integrated circuit chip. The substrate is fabricated of a first material having a first thermal expansivity, and the interposer and integrated circuit chip are fabricated of a... | 05/03/2011 |
| 7936059 | Lead frame packaging technique with reduced noise and cross-talk Broadly speaking, the present invention fills these needs by providing a lead frame package including a substrate stack having opposed sides, one of which includes a plurality of signal traces, with the remaining side including a ground plane. An integrated circuit ... | 05/03/2011 |
| 7915725 | Silicon wafer for semiconductor with powersupply system on the backside of wafer Disclosed is a semiconductor silicon wafer having an electric power supply affixed to the backside of the wafer. By fabricating the electric power supply onto the backside of the wafer that has been left unused, the semiconductor chip can have a self-supplied power,... | 03/29/2011 |
| 7902655 | Multichip package leadframe including electrical bussing Embodiments of the present invention provide electrical bussing for multichip leadframes. In various embodiments, a leadframe may comprise a first die paddle for receiving a first microelectronic device, a second die paddle for receiving a second microelectronic dev... | 03/08/2011 |
| 7902654 | System and method of silicon switched power delivery using a package In one particular embodiment, an integrated circuit includes a package and a substrate electrically and physically coupled to the package. The package includes a first pin, a second pin, and metallization coupling the first pin to the second pin. The substrate is co... | 03/08/2011 |
| 7902656 | Hybrid integrated circuit device, and method for fabricating the same, and electronic device A hybrid integrated circuit device having high mount reliability comprises a module substrate which is a ceramic wiring substrate, a plurality of electronic component parts laid out on the main surface of the module substrate, a plurality of electrode terminals laid... | 03/08/2011 |
| 7893526 | Semiconductor package apparatus A semiconductor package apparatus comprises: at least one semiconductor chip; and a circuit board on which the semiconductor chip is installed, wherein at least one conductive plane for improving power and/or ground characteristics is positioned on a side of the sem... | 02/22/2011 |
| 7888788 | Semiconductor device with reduced cross talk Mutual inductance from an external output signal system to an external input signal system, in which parallel input/output operation is enabled, is reduced. A semiconductor integrated circuit has a plurality of external connection terminals facing a package substrat... | 02/15/2011 |
| 7880286 | Tape wiring substrate and chip-on-film package using the same A chip-on-film package may include a tape wiring substrate, a semiconductor chip mounted on the tape wiring substrate, and a molding compound provided between the semiconductor chip and the tape wiring substrate. The tape wiring substrate may include a film having u... | 02/01/2011 |
| 7872346 | Power plane and land pad feature to prevent human metal electrostatic discharge damage An IC package includes an IC die mounted on a substrate that includes an ESD protection structure formed within the substrate to dissipate any charge accumulation associated with the package's no-connect pins resulting from human body model ESD and/or voltage spikes... | 01/18/2011 |
| 7863724 | Circuit substrate having post-fed die side power supply connections A circuit substrate uses post-fed top side power supply connections to provide improved routing flexibility and lower power supply voltage drop/power loss. Plated-through holes are used near the outside edges of the substrate to provide power supply connections to t... | 01/04/2011 |
| 7863725 | Power device packages and methods of fabricating the same Provided is a power device package including: a substrate including at least one first die attach region; at least one first power semiconductor chip and at least one second power semiconductor chip that are stacked in order on the first die attach region; at least ... | 01/04/2011 |
| 7855447 | Semiconductor integrated circuit device, PDP driver, and plasma display panel In a semiconductor integrated circuit device of the present invention, temperature increase of a bonding wire can be suppressed even when conductive leads are short-circuited with each other, and reliability of the semiconductor integrated circuit device is improved... | 12/21/2010 |
