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| Number | Title | Issue Date |
| 8076760 | Semiconductor fuse arrangements The invention includes semiconductor fuse arrangements containing an electrically conductive plate over and in electrical contact with a plurality of electrically conductive links. Each of the links contacts the electrically conductive plate as a separate region rel... | 12/13/2011 |
| 8072049 | Polysilicon drift fuse A polysilicon resistor fuse has an elongated bow-tie body that is wider at the opposite ends relative to a narrow central portion. The opposite ends of the body of the fuse have high concentrations of N-type dopants to make them low resistance contacts. The upper po... | 12/06/2011 |
| 7834428 | Apparatus and method for reducing noise in mixed-signal circuits and digital circuits Apparatus and a method are provided for reducing noise in mixed-signal and digital circuits. One apparatus (200) includes a metal-oxide-semiconductor field-effect transistor (MOSFET) (210). MOSFET (210) includes a doped substrate (2210) w... | 11/16/2010 |
| 7816768 | Semiconductor device including ground and power-supply planes and a dielectric layer between the ground and power-supply planes A high dielectric loss tangent layer is provided in a dielectric layer between a power-supply plane and a ground plane. The high dielectric loss tangent layer is arranged such that its edge is located between the edge of the power-supply plane and the edge of the gr... | 10/19/2010 |
| 7772680 | Arrangements of fuse-type constructions The invention includes semiconductor fuse arrangements containing an electrically conductive plate over and in electrical contact with a plurality of electrically conductive links. Each of the links contacts the electrically conductive plate as a separate region rel... | 08/10/2010 |
| 7732898 | Electrical fuse and associated methods A fuse link of undoped material is connected between first and second doped material contact regions and a layer of conductive material is located above the first and second contact regions and the fuse link. According to other embodiments, a fuse link is connected ... | 06/08/2010 |
| 7719093 | Circuit board with decoupling capacitors A printed circuit board includes a source interconnect and a ground interconnect, and the circuit board has a two-dimensional geometry having a corner. Protruding portions are provided in circumferences of the source interconnect and the ground interconnect in regio... | 05/18/2010 |
| 7679168 | Printed circuit board with differential pair arrangement A printed circuit board (PCB) with a differential pair arrangement includes a mounting area for receiving a chip, a plurality of first pads located near one edge of the mounting area, a plurality of second pads located near an opposite edge of the mounting area, the... | 03/16/2010 |
| 7642627 | Semiconductor device A semiconductor device includes a semiconductor substrate having an electrode and a conductive pad; a resin projection formed on the semiconductor substrate; and a wiring electrically connected to the electrode, the wiring having a first portion formed on the electr... | 01/05/2010 |
| 7608913 | Noise isolation between circuit blocks in an integrated circuit chip An integrated circuit includes a p-well block region having a high resistivity due to low doping concentration formed in a region of a substrate for providing noise isolation between a first circuit block and a second circuit block. The integrated circuit further in... | 10/27/2009 |
| 7582952 | Method for providing and removing discharging interconnect for chip-on-glass output leads and structures thereof Microelectronic devices may be fabricated while being protected from damage by electrostatic discharge. In one embodiment, a shorting circuit is connected to elements of the microelectronic device, where the microelectronic device is part of a chip-on-glass system. ... | 09/01/2009 |
| 7579673 | Semiconductor device having electrical fuse A semiconductor device includes a semiconductor substrate, and an electrical fuse provided on the semiconductor substrate. The electrical fuse includes a first fuse link and a second fuse link mutually connected in series, a first current inlet/outlet terminal (firs... | 08/25/2009 |
| 7566952 | On-chip circuit pad structure Shielded circuit pad is provided where the parasitic capacitance is tuned out by the inclusion of a shunt transmission line stub which reduces the substrate induced loss in millimeter-wave applications. The circuit pad is located on the substrate, with a shield loca... | 07/28/2009 |
| 7538414 | Semiconductor integrated circuit device Disclosed is a semiconductor IC device capable of suppressing the interference of noise generated in one functional block with other functional blocks therein while protecting against electrostatic breakdown. A plurality of isolated pads are connected to a first ter... | 05/26/2009 |
| 7468546 | Semiconductor device with a noise prevention structure A semiconductor device. The device includes a substrate of the first semiconductor type comprising a pad region and a noise prevention structure in the substrate, on least one side of the pad region. The device further includes the substrate structure, a pad, and a ... | 12/23/2008 |
| 7443020 | Minimizing number of masks to be changed when changing existing connectivity in an integrated circuit Dummy stacks, each providing a common point of connectivity potentially across all metal layers, are incorporated along with the functional block in an integrated circuit. When the connectivity of elements of the functional block need to be changed later, the dummy ... | 10/28/2008 |
| 7413936 | Method of forming copper layers A programmable package with a fuse embedded therein, and fabrication method are provided. The fuse has first and second terminal ends joined by a central portion defining a fusible link. The ends include a portion of the first and second conductive layers, the centr... | 08/19/2008 |
| 7414313 | Polymeric conductor donor and transfer method The present invention relates to a donor laminate for transfer of a conductive layer comprising at least one electronically conductive polymer on to a receiver, wherein the receiver is a component of a device. The present invention also relates to methods pertinent ... | 08/19/2008 |
| 7402442 | Physically highly secure multi-chip assembly A physically secure processing assembly is provided that includes dies mounted on a substrate so as to sandwich the electrical contacts of the dies between the dies and the substrate. The substrate is provided with substrate contacts and conductive pathways that are... | 07/22/2008 |
| 7375982 | Thin film deposition as an active conductor and method therefor A method includes populating components in a cavity of a substrate, disposing a polymer over the components and within the cavity. The polymer is cured and a thin film is formed on the polymer. In addition, a method includes forming an EMI shield within a medical de... | 05/20/2008 |
| 7354805 | Method of making electrically programmable fuse for silicon-on-insulator (SOI) technology A fuse structure and method of forming the same is described, wherein the body of the fuse is formed from a crystalline semiconductor body on an insulator, preferably of a silicon-on-insulator wafer, surrounded by a fill-in dielectric. The fill-in dielectric is pref... | 04/08/2008 |
| 7352050 | Fuse region of a semiconductor region In a fuse region of a semiconductor device, and a method of fabricating the same, the fuse region includes an interlayer insulating layer on a semiconductor substrate, a plurality of fuses on the interlayer insulating layer disposed in parallel with each other, a bl... | 04/01/2008 |
| 7350160 | Method of displaying a guard ring within an integrated circuit The invention displays a guard ring within an integrated circuit design by determining positions of the logic devices within the integrated circuit design, incorporating the guard ring into the integrated circuit design, and displaying the logic devices and the guar... | 03/25/2008 |
| 7348516 | Methods of and laser systems for link processing using laser pulses with specially tailored power profiles A laser pulse with a specially tailored temporal power profile, instead of a conventional temporal shape or substantially square shape, severs an IC link. The specially tailored laser pulse preferably has either an overshoot at the beginning of the laser pulse or a ... | 03/25/2008 |
| 7342317 | Low coefficient of thermal expansion build-up layer packaging and method thereof A build-up layer packaging comprising a first ceramic substrate, a second ceramic substrate, and a circuit layer is provided. The first ceramic substrate has a through hole to dispose a die therein. The second ceramic substrate, attached to a common lower surface of... | 03/11/2008 |
| 7332791 | Electrically programmable polysilicon fuse with multiple level resistance and programming A method to form a programmable resistor device in an integrated circuit device is achieved. The method comprises depositing a semiconductor layer overlying a substrate. The semiconductor layer is patterned to form a plurality of lines. The lines are electrically pa... | 02/19/2008 |
| 7327022 | Assembly, contact and coupling interconnection for optoelectronics A novel micro optical system as a platform technology for electrical and optical interconnections, thermal and mechanical assembly and integration of electronic, optoelectronic, passive and active components. This platform provides optical coupling and chip-to-chip ... | 02/05/2008 |
| 7319267 | Semiconductor device In a prior art, there has been a method in which a power supply line of an output buffer and that of a control circuit are independently provided so that the power supply noise occurring in the control circuit will not affect the output buffer. However, this method ... | 01/15/2008 |
| 7319440 | Organic light emitting diode light source A novel OLED light source and method for controlling said OLED light source panel are disclosed wherein said light source is constructed such that active areas are segmented and said segments are separately addressable. In one embodiment, the segments are a series o... | 01/15/2008 |
| 7313779 | Method and system for tiling a bias design to facilitate efficient design rule checking A method and system for tiling a bias design for an integrated circuit device to facilitate efficient design rule checking. The method is implemented in a computer implemented design synthesis system. The method includes receiving a circuit netlist, wherein the circ... | 12/25/2007 |
| 7310282 | Distributed programmed memory cell overwrite protection A method and circuit for preventing the overprogramming of a memory cell. A fuse circuit is operable to be blown. A combinational logic circuit receives a signal from the fuse circuit, indicating whether or not the fuse has been blown, and controls the programming o... | 12/18/2007 |
| 7309898 | Method and apparatus for providing noise suppression in an integrated circuit A method and apparatus for improving the latchup tolerance of circuits embedded in an integrated circuit while avoiding the introduction of noise from such tolerance into the power rails. ... | 12/18/2007 |
| 7304366 | Self correcting multiple-link fuse An improved fuse link structure and fuse blowing method, the fuse-link structure including a plurality of elongated fuse-link members comprising polysilicon electrically connected in parallel according to a common input Voltage contact and common output current cont... | 12/04/2007 |
| 7291923 | Tapered signal lines In an integrated circuit, a layer including a plurality of conductive wires is described. A first wire, having sidewalls, is tapered from a proximal end which has a first width to a distal end which has a second width, to reduce width from the first width to the sec... | 11/06/2007 |
| 7291902 | Chip component and method for producing a chip component A chip component (1) includes a semiconductor body (2), in which at least one switchable element (6, 62) is arranged in a partial region (24) of the semiconductor body (2). The partial region (24) can be reached by light of ... | 11/06/2007 |
| 7291506 | Magnetic memory device and method of manufacturing the same A method of manufacturing a magnetic memory device includes forming an insulation layer on a substrate, forming a lower electrode on the insulation layer, forming a magneto-resistive film on an upper surface of the lower electrode, the magneto-resistive film includi... | 11/06/2007 |
| 7282751 | Semiconductor device A portion-to-be-melted of a fuse is surrounded by plates, so that heat to be generated in a meltdown portion of the fuse under current supply can be confined or accumulated in the vicinity of the meltdown portion of the fuse. This makes it possible to facilitate mel... | 10/16/2007 |
| 7271012 | Failure analysis methods and systems A method and system for exposing the delicate structures of a device encapsulated in a mold compound such as an integrated circuit (IC). A laser is used to ablate the mold compound and thus remove it, exposing the underlying structure. The laser beam can be steered ... | 09/18/2007 |
| 7245028 | Split control pad for multiple signal A control pad is split into two sections for output one of three signals selected from the group consisted of 00, 01, and 11 on an integrated circuit. Each section is internally connected to different voltage sources, say Vdd which represents logical “1”, or Vss... | 07/17/2007 |
| 7242072 | Electrically programmable fuse for silicon-on-insulator (SOI) technology A fuse structure and method of forming the same is described, wherein the body of the fuse is formed from a crystalline semiconductor body on an insulator, preferably of a silicon-on-insulator wafer, surrounded by a fill-in dielectric. The fill-in dielectric is pref... | 07/10/2007 |
