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| Number | Title | Issue Date |
| 8154107 | Semiconductor device and a method of fabricating the device A semiconductor device having at least one transistor covered by an ultra-stressor layer, and method for fabricating such a device. In an NMOS device, the ultra-stressor layer includes a tensile stress film over the source and drain regions, and a compressive stress... | 04/10/2012 |
| 8102030 | Semiconductor device with strain A semiconductor device includes: a semiconductor substrate having a p-MOS region; an element isolation region formed in a surface portion of the semiconductor substrate and defining p-MOS active regions in the p-MOS region; a p-MOS gate electrode structure formed ab... | 01/24/2012 |
| 8053871 | Implementation of a metal barrier in an integrated electronic circuit A metal barrier is realized on top of a metal portion of a semiconductor product, by forming a metal layer on the surface of the metal portion, with this metal layer comprising a cobalt-based metal material. Then, after an optional deoxidation step, a silicidation s... | 11/08/2011 |
| 8039929 | Asymmetrically stressed CMOS FinFET A CMOS device comprising a FinFET comprises at least one fin structure comprising a source region; a drain region; and a channel region comprising silicon separating the source region from the drain region. The FinFET further comprises a gate region comprising a N+ ... | 10/18/2011 |
| 7977772 | Hybrid metal fully silicided (FUSI) gate A semiconductor device and system for a hybrid metal fully silicided (FUSI) gate structure is disclosed. The semiconductor system comprises a PMOS gate structure, the PMOS gate structure including a first high-κ dielectric layer, a P-metal layer, a mid-gap metal la... | 07/12/2011 |
| 7948063 | Semiconductor device with stress control film utilizing film thickness Semiconductor devices required forming a stress control film to handle different stresses on each side when optimizing the stress on the respective P channel and N channel sections. A unique feature of the semiconductor device of this invention is that P and N chann... | 05/24/2011 |
| 7859088 | Semiconductor device manufacturing method, wafer, and wafer manufacturing method A semiconductor device manufacturing method capable of making in-plane temperature distribution on a wafer uniform at heat treatment time. Before heat treatment is performed by irradiating the wafer with lamp light from the side of a device formed area where semicon... | 12/28/2010 |
| 7759773 | Semiconductor wafer structure with balanced reflectance and absorption characteristics for rapid thermal anneal uniformity Disclosed are embodiments of semiconductor wafer structures and associated methods of forming the structures with balanced reflectance and absorption characteristics. The reflectance and absorption characteristics are balanced by manipulating thin film interferences... | 07/20/2010 |
| 7719090 | Semiconductor device with strain A semiconductor device includes: a semiconductor substrate having a p-MOS region; an element isolation region formed in a surface portion of the semiconductor substrate and defining p-MOS active regions in the p-MOS region; a p-MOS gate electrode structure formed ab... | 05/18/2010 |
| 7482677 | Dielectric structures having high dielectric constants, and non-volatile semiconductor memory devices having the dielectric structures In a method of manufacturing a dielectric structure, after a tunnel oxide layer pattern is formed on a substrate, a floating gate is formed on the tunnel oxide layer. After a first dielectric layer pattern including a metal silicon oxide and a second dielectric laye... | 01/27/2009 |
| 7432216 | Semiconductor device and manufacturing method thereof The technique capable of reducing the power consumption in the MISFET by suppressing the scattering of the carriers due to the fixed charges is provided. A silicon oxynitride film with a physical thickness of 1.5 nm or more and the relative dielectric constant of 4.... | 10/07/2008 |
| 7423330 | Semiconductor device with strain A semiconductor device includes: a semiconductor substrate having a p-MOS region; an element isolation region formed in a surface portion of the semiconductor substrate and defining p-MOS active regions in the p-MOS region; a p-MOS gate electrode structure formed ab... | 09/09/2008 |
| 7414290 | Double gate transistor, method of manufacturing same, and system containing same A double gate transistor comprises a substrate (105, 905) and first and second electrically insulating layers (110, 910), (120, 920). The first and second electrically insulating layers form a fin (130, 930). A first gate dielectric (1... | 08/19/2008 |
| 7400031 | Asymmetrically stressed CMOS FinFET A CMOS device comprising a FinFET comprises at least one fin structure comprising a source region; a drain region; and a channel region comprising silicon separating the source region from the drain region. The FinFET further comprises a gate region comprising a N+ ... | 07/15/2008 |
| 7397073 | Barrier dielectric stack for seam protection The present invention provides a semiconducting device including a gate dielectric atop a semiconducting substrate, the semiconducting substrate containing source and drain regions adjacent the gate dielectric; a gate conductor atop the gate dielectric; a conformal ... | 07/08/2008 |
| 7388278 | High performance field effect transistors on SOI substrate with stress-inducing material as buried insulator and methods The present invention provides a semiconductor structure that includes a high performance field effect transistor (FET) on a semiconductor-on-insulator (SOI) in which the insulator thereof is a stress-inducing material of a preselected geometry. Such a structure ach... | 06/17/2008 |
| 7372107 | SOI chip with recess-resistant buried insulator and method of manufacturing the same A semiconductor-on-insulator structure includes a substrate and a buried insulator stack overlying the substrate. The buried insulator stack includes a first dielectric layer and a recess-resistant layer overlying the first dielectric layer. A second dielectric laye... | 05/13/2008 |
| 7364965 | Semiconductor device and method of fabrication A semiconductor device having a DRAM has a capacitor in which a dielectric film and an upper electrode are laminated on a lower electrode comprising a polysilicone, in which a natural oxide film oxidized by oxygen in the atmosphere grows to at least 1.5 nm on the su... | 04/29/2008 |
| 7358595 | Method for manufacturing MOS transistor Disclosed is a method for fabricating a MOS transistor. The present method includes forming a buffer layer pattern including nitrogen on the semiconductor substrate; forming a gate insulating layer and a gate electrode on the exposed substrate surface; forming a LDD... | 04/15/2008 |
| 7342290 | Semiconductor metal contamination reduction for ultra-thin gate dielectrics A bilayer dielectric structure for substantially reducing or eliminating metal contaminants formed during subsequent polysilicon deposition is provided. The bilayer dielectric structure includes an upper surface region that is rich in chlorine located atop a bottom ... | 03/11/2008 |
| 7332795 | Dielectric passivation for semiconductor devices A semiconductor device is disclosed that includes a layer of Group III nitride semiconductor material that includes at least one surface, a control contact on the surface for controlling the electrical response of the semiconductor material, a dielectric barrier lay... | 02/19/2008 |
| 7329953 | Structure for reducing leakage currents and high contact resistance for embedded memory and method for making same A method for fabricating an insulating layer having contact openings of varying depths for logic/DRAM circuits is achieved using a single mask and etch step. After forming stacked or trench capacitors, a planar insulating layer is formed. Contact openings are etched... | 02/12/2008 |
| 7300891 | Method and system for increasing tensile stress in a thin film using multi-frequency electromagnetic radiation A method and system are described for increasing the tensile stress in thin films formed on a substrate, such as silicon nitride films. The thin film may be a planar film, or a non-planar film, such as a nitride film formed over a NMOS gate. The thin film is exposed... | 11/27/2007 |
| 7300855 | Reversible oxidation protection of microcomponents In a method for the reversible oxidation protection of microcomponents, a substrate is provided, a silicon nitride layer is provided on the substrate in order to protect it against oxidation, an insulation layer is applied to the silicon nitride layer, and a reoxida... | 11/27/2007 |
| 7301219 | Electrically erasable programmable read only memory (EEPROM) cell and method for making the same An asymmetrically doped memory cell has first and second N+ doped junctions on a P substrate. A composite charge trapping layer is disposed over the P substrate and between the first and the second N+ doped junctions. A N− doped region is positioned adjacent to th... | 11/27/2007 |
| 7265066 | Method and system for increasing tensile stress in a thin film using collimated electromagnetic radiation A method and system are described for increasing the tensile stress in thin films formed on a substrate, such as silicon nitride films. The thin film may be a planar film, or a non-planar film, such as a nitride film formed over a NMOS gate. The thin film is exposed... | 09/04/2007 |
| 7253481 | High performance MOS device with graded silicide A semiconductor device suffering fewer current crowding effects and a method of forming the same are provided. The semiconductor device includes a substrate, a gate over the substrate, a gate spacer along an edge of the gate and overlying a portion of the substrate,... | 08/07/2007 |
| 7253455 | pHEMT with barrier optimized for low temperature operation In one embodiment, a semiconductor device (500) includes a buffer layer (504) formed over a substrate (502). An AlxGa1−xAs layer (506) is formed over the buffer layer (504) and has a first doped region (5... | 08/07/2007 |
| 7244644 | Undercut and residual spacer prevention for dual stressed layers Methods are disclosed for forming dual stressed layers in such a way that both undercutting and an undesirable residual spacer of the first-deposited stressed layer are prevented. In one embodiment, a method includes forming a first stressed silicon nitride layer ov... | 07/17/2007 |
| 7208812 | Semiconductor device having STI without divot and its manufacture The method of manufacturing a semiconductor device has the steps of: etching a semiconductor substrate to form an isolation trench by using as a mask a pattern including a first silicon nitride film and having a window; depositing a second silicon nitride film cover... | 04/24/2007 |
| 7192855 | PECVD nitride film A method for forming a semiconductor device is provided. In accordance with the method, a substrate (103) is provided, and a dielectric material (123) is formed on the substrate through plasma enhanced chemical vapor deposition (PECVD). The PECVD is co... | 03/20/2007 |
| 7187084 | Damascene method employing composite etch stop layer A damascene structure is provided comprising a substrate, a lower intermetal dielectric layer over the substrate, an exposed conductive structure within the lower intermetal dielectric layer, a composite etch stop layer over the lower intermetal dielectric layer and... | 03/06/2007 |
| 7179749 | Method for fabricating semiconductor device capable of decreasing critical dimension in peripheral region A method for fabricating a semiconductor device where a critical dimension in a peripheral region is decreased. The method includes the steps of: forming a silicon nitride layer on a substrate including a cell region and a peripheral region; forming a silicon oxynit... | 02/20/2007 |
| 7173274 | Incorporation of carbon in silicon/silicon germanium epitaxial layer to enhance yield for Si-Ge bipolar technology A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe bas... | 02/06/2007 |
| 7166891 | Semiconductor device with etch resistant electrical insulation layer between gate electrode and source electrode A trench-structure semiconductor device is highly reliable and has an increased resistance to hydrofluoric acid cleaning or other cleaning of an insulation film between a gate electrode, which is embedded in a trench, and source electrode. In a trench-structure semi... | 01/23/2007 |
| 7163853 | Method of manufacturing a capacitor and a metal gate on a semiconductor device A method of manufacturing a capacitor and a metal gate on a semiconductor device comprises forming a dummy gate on a substrate, forming a trench layer on the substrate and adjacent the dummy gate, forming a capacitor trench in the trench layer, forming a bottom elec... | 01/16/2007 |
| 7154125 | Nitride-based semiconductor light-emitting device and manufacturing method thereof The nitride-based semiconductor light-emitting device and manufacturing method thereof are disclosed: the nitride-based semiconductor light-emitting device includes a reflective layer formed on a support substrate, a p-type nitride-based semiconductor layer, a light... | 12/26/2006 |
| 7148158 | Semiconductor device and method for manufacturing the same A semiconductor device includes a semiconductor device comprising a semiconductor substrate, source/drain regions formed in the semiconductor substrate, a gate insulation film formed on the semiconductor substrate, a gate electrode formed on the gate insulation film... | 12/12/2006 |
| 7141850 | Gated semiconductor assemblies and methods of forming gated semiconductor assemblies In one aspect, the invention includes a method of forming a gated semiconductor assembly, comprising: a) forming a silicon nitride layer over and against a floating gate; and b) forming a control gate over the silicon nitride layer. In another aspect, the invention ... | 11/28/2006 |
| 7135410 | Etch with ramping A method for etching a feature in an etch layer through a mask over a substrate. The substrate is placed in a process chamber. An etch plasma is provided to the process chamber, where the etch plasma begins to etch. A feature is etched in the etch layer with the etc... | 11/14/2006 |
