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| Number | Title | Issue Date |
| 7834427 | Integrated circuit having a semiconductor arrangement An integrated circuit including a semiconductor arrangement, a power semiconductor component and an associated production method is disclosed. One embodiment includes a carrier substrate, a first interconnect layer, formed on the carrier substrate and has at least o... | 11/16/2010 |
| 7550823 | Nonvolatile memory cell, array thereof, fabrication methods thereof and device comprising the same A nonvolatile memory cell is capable of reducing an excessive current leakage due to a rough surface of a polysilicon and of performing even at a low temperature process by forming the first oxide film including a silicon oxynitride (SiOxNy) layer using nitrous oxid... | 06/23/2009 |
| 7432216 | Semiconductor device and manufacturing method thereof The technique capable of reducing the power consumption in the MISFET by suppressing the scattering of the carriers due to the fixed charges is provided. A silicon oxynitride film with a physical thickness of 1.5 nm or more and the relative dielectric constant of 4.... | 10/07/2008 |
| 7420264 | High reflector tunable stress coating, such as for a MEMS mirror An optical device having a high reflector tunable stress coating includes a micro-electromechanical system (MEMS) platform, a mirror disposed on the MEMS platform, and a multiple layer coating disposed on the mirror. The multiple layer coating includes a layer of si... | 09/02/2008 |
| 7372114 | Semiconductor device, and method of fabricating the same A silicon oxynitride film is manufactured using SiH4, N2O and H2 by plasma CVD, and it is applied to the gate insulating film (1004 in FIG. 1A) of a TFT. The characteristics of the silicon oxynitride film are controlled... | 05/13/2008 |
| 7372113 | Semiconductor device and method of manufacturing the same Disclosed is a semiconductor device comprising a semiconductor substrate, a gate electrode, a first insulating film formed between the semiconductor substrate and the gate electrode, and a second insulating film formed along a top surface or a side surface of the ga... | 05/13/2008 |
| 7358595 | Method for manufacturing MOS transistor Disclosed is a method for fabricating a MOS transistor. The present method includes forming a buffer layer pattern including nitrogen on the semiconductor substrate; forming a gate insulating layer and a gate electrode on the exposed substrate surface; forming a LDD... | 04/15/2008 |
| 7329956 | Dual damascene cleaning method A semiconductor structure having a pore sealed portion of a dielectric layer is provided. Exposed pores of the dielectric material are sealed using an anisotropic plasma so that pores along the bottom of the opening are sealed, and pores along sidewalls of the openi... | 02/12/2008 |
| 7319270 | Multi-layer electrode and method of forming the same An interconnect includes an opening formed in a dielectric layer. A conductive barrier is deposited in the opening, over which a first conductive layer is deposited. A conductive oxide is deposited over the first conductive layer, and a second conductive layer, form... | 01/15/2008 |
| 7309920 | Chip structure and process for forming the same A chip or wafer comprises a semiconductor substrate, first and second transistors on the semiconductor substrate, first and second metal layers over the semiconductor substrate, an insulating layer on the first and second metal layers, a third and fourth metal layer... | 12/18/2007 |
| 7302982 | Label applicator and system A label applicator including a support surface having a central area and curving downwardly from the central area. A post assembly extends up from the central area such that a label having a label through-hole can be positioned in a support position generally on the... | 12/04/2007 |
| 7301219 | Electrically erasable programmable read only memory (EEPROM) cell and method for making the same An asymmetrically doped memory cell has first and second N+ doped junctions on a P substrate. A composite charge trapping layer is disposed over the P substrate and between the first and the second N+ doped junctions. A N− doped region is positioned adjacent to th... | 11/27/2007 |
| 7285314 | Steam barrier film A steam barrier film comprising at least one inorganic gas barrier layer on a polyalkylene naphthalate resin substrate film in which the glass transition temperature (Tg) of the polyalkylene naphthalate resin is from 70 to 150° C. and the steam barrier film compris... | 10/23/2007 |
| 7262432 | Semiconductor device and fabrication method thereof A hydrogenation method that utilizes plasma directly exposes a crystalline semiconductor film to the plasma, and therefore involves the problem that the crystalline semiconductor film is damaged by the ions generated simultaneously in the plasma. If a substrate is h... | 08/28/2007 |
| 7256087 | Techniques for improving negative bias temperature instability (NBTI) lifetime of field effect transistors In one embodiment, an integrated circuit includes a PMOS transistor having a gate stack comprising a P+ doped gate polysilicon layer and a nitrided gate oxide (NGOX) layer. The NGOX layer may be over a silicon substrate. The integrated circuit further includes an in... | 08/14/2007 |
| 7253501 | High performance metallization cap layer A semiconductor device having a nonconductive cap layer comprising a first metal element. The nonconductive cap layer comprises a first metal nitride, a first metal oxide, or a first metal oxynitride over conductive lines and an insulating material between the condu... | 08/07/2007 |
| 7244520 | Substrate for nitride semiconductor growth A substrate for growth of nitride semiconductor capable of obtaining a high-quality nitride semiconductor crystal layer is provided. A substrate for growth of nitride semiconductor for growth of a nitride semiconductor layer on a sapphire substrate (1) accord... | 07/17/2007 |
| 7244644 | Undercut and residual spacer prevention for dual stressed layers Methods are disclosed for forming dual stressed layers in such a way that both undercutting and an undesirable residual spacer of the first-deposited stressed layer are prevented. In one embodiment, a method includes forming a first stressed silicon nitride layer ov... | 07/17/2007 |
| 7242012 | Lithography device for semiconductor circuit pattern generator General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor ... | 07/10/2007 |
| 7226834 | PMD liner nitride films and fabrication methods for improved NMOS performance Semiconductor devices (102) and fabrication methods (10) are provided, in which a nitride film (130) is formed over NMOS transistors to impart a tensile stress in all or a portion of the NMOS transistor to improve carrier mobility. The nitride l... | 06/05/2007 |
| 7223696 | Methods for maskless lithography General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor ... | 05/29/2007 |
| 7220489 | Layered structures for optical reflectors Device of layered structures for optical reflectors and method for making the device. A device for providing environmental stability and mechanical integrity in space includes a substrate and a first silicon oxynitride layer on the substrate. The first silicon oxyni... | 05/22/2007 |
| 7217989 | Composition for selectively polishing silicon nitride layer and polishing method employing it To provide a polishing composition whereby the stock removal rate of a silicon nitride layer is higher than the stock removal rate of a silicon oxide layer, there is substantially no adverse effect against polishing planarization, and a sufficient stock removal rate... | 05/15/2007 |
| 7208400 | Method of manufacturing a semiconductor device including a dielectric film formed between first and second electrode layers There are provided a gate dielectric film formed on a semiconductor substrate; a gate electrode including: a first electrode layer formed on the gate dielectric film, a dielectric film having a thickness of 5 Å or more and 100 Å or less, and formed on the first ... | 04/24/2007 |
| 7208426 | Preventing plasma induced damage resulting from high density plasma deposition A method and apparatus for preventing plasma induced damage resulting from high density plasma deposition processes. In the present embodiment, Un-doped Silica Glass(USG) is deposited so as to form a USG liner. In the present embodiment, the USG liner directly overl... | 04/24/2007 |
| 7202568 | Semiconductor passivation deposition process for interfacial adhesion A method of passivating an integrated circuit (IC) is provided. An insulating layer is formed onto the IC. An adhesion layer is formed onto a surface of the insulating layer by treating the surface of the insulating layer with a gas. A first passivation layer is for... | 04/10/2007 |
| 7202551 | Display device having underlying insulating film and insulating films A resin material having low dielectric constant is used as an inter-layer insulating film and its bottom surface is contacted with a silicon oxide film across the whole surface thereof. Thereby, the surface may be flattened and capacity produced between a thin film ... | 04/10/2007 |
| 7202164 | Method of forming ultra thin silicon oxynitride for gate dielectric applications A method of forming a gate dielectric layer is disclosed. The method comprises the following steps. A substrate is provided having silicon regions containing surfaces upon which gate dielectrics are to be disposed. An oxide is formed over the surfaces. A silicon lay... | 04/10/2007 |
| 7195716 | Etching process and patterning process An etching process is described. A material layer having a bottom anti-reflection coating (BARC) and a patterned photoresist layer thereon is provided. An etching step is performed to the BARC using the patterned photoresist layer as a mask. A cleaning step is perfo... | 03/27/2007 |
| 7192894 | High performance CMOS transistors using PMD liner stress A silicon nitride layer (110) is formed over a transistor gate (40) and source and drain regions (70). The as-formed silicon nitride layer (110) comprises a first tensile stress and a high hydrogen concentration. The as-formed silicon nit... | 03/20/2007 |
| 7193239 | Three dimensional structure integrated circuit A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, red... | 03/20/2007 |
| 7190033 | CMOS device and method of manufacture A CMOS device and manufacturing method thereof wherein a bilayer etch stop is used over a PMOS transistor, and a single etch stop layer is used for an NMOS transistor, for forming contacts to the source or drain of the CMOS device. A surface tension-reducing layer i... | 03/13/2007 |
| 7190024 | Method of manufacturing a thin dielectric layer using a heat treatment and a semiconductor device formed using the method In a method for forming a semiconductor device and a semiconductor device formed in accordance with the method, a thin dielectric layer is provided between a lower conductive layer and an upper conductive layer. In one embodiment, the thin dielectric layer comprises... | 03/13/2007 |
| 7187038 | Semiconductor device with MOS transistors with an etch-stop layer having an improved residual stress level and method for fabricating such a semiconductor device A semiconductor device includes a substrate, MOS transistors in the substrate, and a dielectric layer on the MOS transistors. Contact holes are formed through the dielectric layer to provide electrical connection to the MOS transistors. An etch-stop layer is between... | 03/06/2007 |
| 7176545 | Apparatus and methods for maskless pattern generation General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor ... | 02/13/2007 |
| 7176499 | Method of manufacturing a semiconductor light emitting device, semiconductor light emitting device, method of manufacturing a semiconductor device, semiconductor device, method of manufacturing a device, and device When a semiconductor light emitting device or a semiconductor device is manufactured by growing nitride III-V compound semiconductor layers, which will form a light emitting device structure or a device structure, on a nitride III-V compound semiconductor substrate ... | 02/13/2007 |
| 7173339 | Semiconductor device having a substrate an undoped silicon oxide structure and an overlaying doped silicon oxide structure with a sidewall terminating at the undoped silicon oxide structure An etchant including C2HxFy, where x is an integer from two to five, inclusive, where y is an integer from one to four, inclusive, and where x plus y equals six, etches doped silicon dioxide with selectivity over both undoped silicon... | 02/06/2007 |
| 7169682 | Method for manufacturing semiconductor device A method for manufacturing a semiconductor device comprising: a first step of successively forming a silicon oxide film and a silicon nitride film on a silicon substrate, followed by forming a silicon nitride oxide film or a multil... | 01/30/2007 |
| 7166899 | Semiconductor device, and method of fabricating the same A silicon oxynitride film is manufactured using SiH4, N2O and H2 by plasma CVD, and it is applied to the gate insulating film (1004 in FIG. 1A) of a TFT. The characteristics of the silicon oxynitride film are controlled... | 01/23/2007 |
| 7160818 | Semiconductor device and method for fabricating same An aspect of the present invention includes; a silicon oxynitride film having an oxynitride layer which is formed on at least the surface of a silicon substrate and in which nitrogen atoms are in a three-coordinate bond state, and a silicon oxide layer which is form... | 01/09/2007 |
