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| Number | Title | Issue Date |
| 8178952 | Method of forming high-k dual dielectric stack The present invention discloses a method including: providing a Group III-V component semiconductor material; forming a first layer over a surface of the Group III-V component semiconductor material, the first layer to unpin a Fermi level at the surface; forming a s... | 05/15/2012 |
| 8138579 | Structures and methods of forming SiGe and SiGeC buried layer for SOI/SiGe technology Semiconductor structures and methods of forming semiconductor structures, and more particularly to structures and methods of forming SiGe and/or SiGeC buried layers for SOI/SiGe devices. An integrated structure includes discontinuous, buried layers having alternatin... | 03/20/2012 |
| 8035202 | Electronic device having a wiring substrate A semiconductor chip of the present invention has a wiring substrate and a chip part. The wiring substrate has an insulating resin layer having a first major surface and a second major surface, and a first wiring layer disposed on the insulating resin layer on the s... | 10/11/2011 |
| 7968977 | Dicing film having shrinkage release film and method of manufacturing semiconductor package using the same The present invention relates to a dicing film having an adhesive film for dicing a wafer and a die adhesive film, which are used for manufacturing a semiconductor package, and a method of manufacturing a semiconductor package using the same. More particularly, the ... | 06/28/2011 |
| 7911037 | Method and structure for creating embedded metal features A method and structure for creating embedded metal features includes embedded trace substrates wherein bias and signal traces are embedded in a first surface of the embedded trace substrate and extend into the body of the embedded trace substrate. The bias trace and... | 03/22/2011 |
| 7859087 | Semiconductor device A semiconductor device includes: a semiconductor layer; at least one electrode formed on a semiconductor layer to be in contact with the semiconductor layer; and a passivation film covering the semiconductor layer and at least part of the top surface of the electrod... | 12/28/2010 |
| 7851891 | Semiconductor device and method for fabricating the same A method for fabricating a semiconductor device includes the steps of: forming a first insulating film on a semiconductor substrate; removing part of the first insulating film; forming a second insulating film having a leakage current density higher than that of the... | 12/14/2010 |
| 7834426 | High-k dual dielectric stack The present invention discloses a method including: providing a Group III-V component semiconductor material; forming a first layer over a surface of the Group III-V component semiconductor material, the first layer to unpin a Fermi level at the surface; forming a s... | 11/16/2010 |
| 7829978 | Closed loop CESL high performance CMOS device An N-MOS and/or P-MOS device having enhanced performance such as an FET suitable for use in a CMOS circuit. The device comprises both an “L-like” shaped layer or spacer on the side walls of a gate structure as well as a CESL (contact-etch stop layer) that covers... | 11/09/2010 |
| 7714414 | Method and apparatus for polymer dielectric surface recovery by ion implantation In one embodiment, the disclosure relates to a method and apparatus for surface recovery of a polymer insulation layer through implantation. The method includes providing a substrate having thereon a conductive pad and an insulation layer, optionally processing the ... | 05/11/2010 |
| 7656010 | Semiconductor device A semiconductor device includes: a semiconductor layer; at least one electrode formed on a semiconductor layer to be in contact with the semiconductor layer; and a passivation film covering the semiconductor layer and at least part of the top surface of the electrod... | 02/02/2010 |
| 7652354 | Semiconductor devices and methods of manufacturing semiconductor devices Disclosed is a semiconductor device and a method of manufacturing a semiconductor device. A semiconductor device may include an insulating layer and a metal interconnection. An insulating layer may include a first layer including fluorine and a second layer includin... | 01/26/2010 |
| 7638859 | Interconnects with harmonized stress and methods for fabricating the same Interconnects with harmonized stress and methods for fabricating the same. An interconnect comprises a substrate having a conductive member. A composite low-k dielectric layer interposed with at least one stress-harmonizing layer therein overlies the substrate. A co... | 12/29/2009 |
| 7589398 | Embedded metal features structure A method and structure for creating embedded metal features includes embedded trace substrates wherein bias and signal traces are embedded in a first surface of the embedded trace substrate and extend into the body of the embedded trace substrate. The bias trace and... | 09/15/2009 |
| 7489020 | Semiconductor wafer assemblies An elevated containment structure in the shape of a wafer edge ring surrounding a surface of a semiconductor wafer is disclosed, as well as methods of forming and using such a structure. In one embodiment, a wafer edge ring is formed using a stereolithography (STL) ... | 02/10/2009 |
| 7436009 | Via structures and trench structures and dual damascene structures Via hole and trench structures and fabrication methods are disclosed. The structure includes a conductive layer in a dielectric layer, and a via structure in the dielectric layer contacting a portion of a surface of the conductive layer. The via structure includes t... | 10/14/2008 |
| 7425763 | Electronic circuit package An electronic apparatus which includes a wiring substrate which includes wiring conductors, and a plurality of semiconductor bare chips that are formed on the wiring substrate. The semiconductor bare chips include a processor for processing data and a circuit having... | 09/16/2008 |
| 7422927 | Methods of forming a resistance variable element The invention includes methods of depositing silver onto a metal selenide-comprising surface, and methods of forming a resistance variable device. In one implementation, a method of depositing silver onto a metal selenide-comprising surface includes providing a depo... | 09/09/2008 |
| 7420264 | High reflector tunable stress coating, such as for a MEMS mirror An optical device having a high reflector tunable stress coating includes a micro-electromechanical system (MEMS) platform, a mirror disposed on the MEMS platform, and a multiple layer coating disposed on the mirror. The multiple layer coating includes a layer of si... | 09/02/2008 |
| 7410899 | Defectivity and process control of electroless deposition in microelectronics applications Methods and compositions for electrolessly depositing Co, Ni, or alloys thereof onto a substrate in manufacture of microelectronic devices. Grain refiners, levelers, oxygen scavengers, and stabilizers for electroless Co and Ni deposition solutions. ... | 08/12/2008 |
| 7405466 | Method of fabricating microelectromechanical system structures A method of simultaneously bonding components, comprising the following steps. At least first, second and third components are provided and comprise: at least one glass component; and at least one conductive or semiconductive material component. The order of stackin... | 07/29/2008 |
| 7397073 | Barrier dielectric stack for seam protection The present invention provides a semiconducting device including a gate dielectric atop a semiconducting substrate, the semiconducting substrate containing source and drain regions adjacent the gate dielectric; a gate conductor atop the gate dielectric; a conformal ... | 07/08/2008 |
| 7396718 | Technique for creating different mechanical strain in different channel regions by forming an etch stop layer stack having differently modified intrinsic stress A technique is provided that allows the formation of contact etch stop layers having different intrinsic stress for different transistors, while substantially avoiding any device degradation owing to the partial removal of the contact etch stop layer. Hereby, an add... | 07/08/2008 |
| 7396777 | Method of fabricating high-k dielectric layer having reduced impurity Methods of fabricating high-k dielectric layers having reduced impurities for use in semiconductor applications are disclosed. The methods include the steps of: forming a stacked dielectric layer having a first dielectric layer and a second dielectric layer formed o... | 07/08/2008 |
| 7391094 | Semiconductor structure and method of making same A semiconductor structure includes a substrate having a surface and being made of a material that provides atypical surface properties to the surface, a bonding layer on the surface of the substrate, and a further layer molecularly bonded to the bonding layer. A met... | 06/24/2008 |
| 7391116 | Fretting and whisker resistant coating system and method A coated electrically conductive substrate has particular utility where there are multiple closely spaced leads and tin whiskers constitute a potential short circuit. This electrically conductive substrate has a plurality of leads separated by a distance capable of ... | 06/24/2008 |
| 7371633 | Dielectric layer for semiconductor device and method of manufacturing the same A semiconductor device comprises a silicate interface layer and a high-k dielectric layer overlying the silicate interface layer. The high-k dielectric layer comprises metal alloy oxides. ... | 05/13/2008 |
| 7372157 | Semiconductor device including titanium wires and manufacturing method therefor A first insulating film consisting of an insulating material is formed on a major surface of a semiconductor substrate. On the first insulating film, a wire comprising a first conductive layer, which contains one of elemental Ti and a Ti compound, is formed. Cover f... | 05/13/2008 |
| 7372200 | Light-emitting device, method of manufacturing a light-emitting device, and electronic equipment The present invention uses plastic film in vacuum sealing an OLED. Inorganic insulating films which can prevent oxygen or water from being penetrated therein and an organic insulating film which has a smaller internal stress than that of the inorganic insulating fil... | 05/13/2008 |
| 7368804 | Method and apparatus of stress relief in semiconductor structures A method, apparatus and system are provided for relieving stress in the via structures of semiconductor structures whenever a linewidth below a via is larger than a ground-rule, including providing a via at least as large as the groundrule, providing a landing pad a... | 05/06/2008 |
| 7365006 | Semiconductor package and substrate having multi-level vias fabrication method A semiconductor package and substrate having multi-level plated vias provide a high density blind via solution at low incremental cost. Via are half-plated atop a circuit pattern and then a second via half is added to complete the via after isolation of elements of ... | 04/29/2008 |
| 7358568 | Low resistance semiconductor process and structures A process for forming a semiconductor device comprises the steps of providing a semiconductor substrate assembly comprising a semiconductor wafer having an active area formed therein, a plurality of transistor gates each having a TEOS cap thereon and a pair of nitri... | 04/15/2008 |
| 7358590 | Semiconductor device and driving method thereof A semiconductor device includes a memory with a simple structure, an inexpensive semiconductor device, a manufacturing method and a driving method thereof. One feature is that, in a memory which has a layer including an organic compound as a dielectric, by applying ... | 04/15/2008 |
| 7358587 | Semiconductor structures In one aspect, the invention includes a method of forming a material within an opening, comprising: a) forming an etch-stop layer over a substrate, the etch-stop layer having an opening extending therethrough to expose a portion of the underlying substrate and compr... | 04/15/2008 |
| 7355268 | High reflector tunable stress coating, such as for a MEMS mirror An optical device having a high reflector tunable stress coating includes a micro-electromechanical system (MEMS) platform, a mirror disposed on the MEMS platform, and a multiple layer coating disposed on the mirror. The multiple layer coating includes a layer of si... | 04/08/2008 |
| 7352053 | Insulating layer having decreased dielectric constant and increased hardness A method of manufacturing a mechanically robust insulating layer, including forming a low-k dielectric layer having a first dielectric constant on a substrate and forming a carbon nitride cap layer on the low-k dielectric layer, the insulating layer thereby having a... | 04/01/2008 |
| 7348599 | Semiconductor device and manufacturing method thereof A p channel TFT of a driving circuit has a single drain structure and its n channel TFT, a GOLD structure or an LDD structure. A pixel TFT has the LDD structure. A pixel electrode disposed in a pixel portion is connected to the pixel TFT through a hole bored in at l... | 03/25/2008 |
| 7342804 | Ball grid array resistor capacitor network An R-C network formed on a substrate. The capacitor includes a metal member with anodized and unanodized layers. The unanodized layer functions as one of the capacitor's electrodes. The anodized layer functions as the capacitor's dielectric layer. The resistor is fo... | 03/11/2008 |
| 7332795 | Dielectric passivation for semiconductor devices A semiconductor device is disclosed that includes a layer of Group III nitride semiconductor material that includes at least one surface, a control contact on the surface for controlling the electrical response of the semiconductor material, a dielectric barrier lay... | 02/19/2008 |
| 7332796 | Devices and methods of preventing plasma charging damage in semiconductor devices Methods for protecting semiconductor devices from plasma charging damage are disclosed. An example disclosed method includes depositing an etching stop layer on a substrate with at least one predetermined structure; depositing a premetallic dielectric layer and a ch... | 02/19/2008 |
