Quotables
"Radio has no future."
Lord Kelvin, British mathematician and physicist ; 1897
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7968976 | Guard ring extension to prevent reliability failures An embodiment of the present invention is a technique to prevent reliability failures in semiconductor devices. A trench is patterned in a polyimide layer over a guard ring having a top metal layer. A passivation layer is etched at bottom of the trench. A capping la... | 06/28/2011 |
| 7915712 | Structures including passivated germanium A method of passivating germanium that comprises providing a germanium material and carburizing the germanium material to form a germanium carbide material. The germanium carbide material may be formed by microwave plasma-enhanced chemical vapor deposition by exposi... | 03/29/2011 |
| 7888779 | Method of fabrication InGaAIN film and light-emitting device on a silicon substrate There is provided a method of fabricating InGaAlN film on a silicon substrate, which comprises the following steps of forming a pattern structured having grooves and mesas on the silicon substrate, and depositing InGaAlN film on the surface of substrate, wherein the... | 02/15/2011 |
| 7745908 | Semiconductor component containing compound of aluminum, gallium, indium, arsenic, and antimony has mesa structure whose sides have passivation layer of compound of aluminum, gallium, arsenic, and antimony A Semiconductor component that contains AlxGayIn1-x-yAszSb1-z, whereby the parameters x, y, and z are selected such that a bandgap of less than 350 meV is achieved, whereby it features a mesa-structuring and a p... | 06/29/2010 |
| 7642626 | Semiconductor devices including mesa structures and multiple passivation layers A semiconductor device including a semiconductor structure defining a mesa having a mesa surface and mesa sidewalls, and first and second passivation layers. The first passivation layer may be on at least portions of the mesa sidewalls, at least a portion of the mes... | 01/05/2010 |
| 7432582 | Method of forming a through-substrate interconnect A method of manufacturing a microelectronics device is provided, wherein the microelectronics device is formed on a substrate having a frontside and a backside. The method comprises forming a circuit element on the frontside of the substrate from a plurality of laye... | 10/07/2008 |
| 7423291 | Semiconductor device and electronic device A channel forming region of a thin-film transistor is covered with an electrode and wiring line that extends from a source line. As a result, the channel forming region is prevented from being illuminated with light coming from above the thin-film transistor, whereb... | 09/09/2008 |
| 7345368 | Semiconductor device and the manufacturing method for the same A semiconductor device has a semiconductor substrate having first and second surface, a first resin film formed on the first surface of the semiconductor substrate and a second resin film formed on the second surface of the semiconductor substrate. A projection elec... | 03/18/2008 |
| 7245002 | Semiconductor substrate having a stepped profile A semiconductor substrate which effectively prevents a chipping phenomenon, wherein the outer peripheral extremity of the insulation layer is located between the outer peripheral extremity of the semiconductor layer and the outer peripheral extremity of the support ... | 07/17/2007 |
| 7192888 | Low selectivity deposition methods A deposition method includes forming a nucleation layer over a substrate, forming a layer of a first substance at least one monolayer thick chemisorbed on the nucleation layer, and forming a layer of a second substance at least one monolayer thick chemisorbed on the... | 03/20/2007 |
| 7193301 | Semiconductor device and manufacturing method thereof A plurality of semiconductor chips (14) each having a first main surface (14b) formed with electrode pads (21) and a second main surface (14c) opposite to the first main surface are respectively mounted on a chip mounting su... | 03/20/2007 |
| 7187058 | Semiconductor component having a pn junction and a passivation layer applied on a surface The invention relates to a semiconductor component having a semiconductor body (100) and at least one pn junction present in the semiconductor body (100) and an amorphous passivation layer (70) arranged at least in sections on a surface (101 | 03/06/2007 |
| 7166861 | Thin-film transistor and method for manufacturing the same The present invention provides a thin-film transistor that is formed by using a patterning method capable of forming a semiconductor channel layer in sub-micron order and a method for manufacturing thereof that provides a thin-film transistor with a larger area, and... | 01/23/2007 |
| 7112545 | Passivation of material using ultra-fast pulsed laser The surface of a semiconductor material, e.g., gallium arsenide, is passivated by irradiating the surface with ultra-short laser pulses, until a stable passive surface is achieved. The passive surface so prepared is devoid of a superficial oxide layer. ... | 09/26/2006 |
| 7054469 | Passivation layer structure A conductor layer is patterned into flat portions, for example of a fingerprint sensor that effects capacitive measurement. The conductor layer is fragmented in a lattice-like manner by cutouts so that an applied passivation layer rests on a base layer that is prese... | 05/30/2006 |
| 6992325 | Active matrix organic electroluminescence display device An active matrix organic electroluminescence display device capable of maintaining the brightness of the organic light emitting diode. The active matrix organic electroluminescence display device comprises a thin film transistor and an organic light emitting diode. ... | 01/31/2006 |
| 6979877 | Solid-state device A method of making dielectrically isolated solid state device comprising state device (including integrated circuits) comprises providing a silicon wafer having a PN junction or other electronic rectifying barrier contained therein and thermally growing or ion-impla... | 12/27/2005 |
| 6972477 | Circuit device with conductive patterns separated by insulating resin-filled grooves To make thin a circuit device 10 in which are incorporated a plurality of types of circuit elements 12 that differ in thickness, first conductive patterns, onto which comparatively thin circuit elements 12A are mounted, are formed thickly, and s... | 12/06/2005 |
| 6936868 | Sequential mesa avalanche photodiode capable of realizing high sensitization and method of manufacturing the same A sequential mesa type avalanche photodiode (APD) includes a semiconductor substrate and a sequential mesa portion formed on the substrate. In the sequential mesa portion, a plurality of semiconductor layers, including a light absorbing layer and a multiplying layer... | 08/30/2005 |
| 6924197 | Method of fabricating an integrated circuit with a dielectric layer exposed to a hydrogen-bearing nitrogen source The present invention provides a flash memory integrated circuit and a method of fabricating the same. A tunnel dielectric in an erasable programmable read only memory (EPROM) device is nitrided with a hydrogen-bearing compound, particularly ammonia. Hydrogen is thu... | 08/02/2005 |
| 6921937 | Integrated circuit with a dielectric layer exposed to a hydrogen-bearing nitrogen source The present invention provides a flash memory integrated circuit and a method of fabricating the same. A tunnel dielectric in an erasable programmable read only memory (EPROM) device is nitrided with a hydrogen-bearing compound, particularly ammonia. Hydrogen is thu... | 07/26/2005 |
| 6906401 | Method to fabricate high-performance NPN transistors in a BiCMOS process A method of forming a quasi-self-aligned heterojunction bipolar transistor (HBT) that exhibits high-performance is provided. The method includes the use of a patterned emitter landing pad stack which serves to improve the alignment for the emitter-opening lithograph... | 06/14/2005 |
| 6900523 | Termination structure for MOSgated power devices The termination of a MOSgated device is formed by a trench bevel which surrounds the active device area. The trench bevel has flat walls which extend into and through the epitaxial layer containing the active area which has a lateral extend equal to or less than the... | 05/31/2005 |
| 6888171 | Light emitting diode A semi-conductor light emitting diode includes closely spaced n and p electrodes formed on the same side of a substrate to form an LED with a small foot-print. A semi-transparent U shaped p contact layer is formed along three sides of the top surface of the underlyi... | 05/03/2005 |
| 6882031 | Ammonia gas passivation on nitride encapsulated devices A passivation method includes disassociating ammonia so as to expose at least interfaces between silicon-containing and passivation structures to at least hydrogen species derived from the ammonia and forming an encapsulant layer that is positioned so as to substant... | 04/19/2005 |
| 6883159 | Patterning semiconductor layers using phase shifting and assist features A photomask and method of patterning a photosensitive layer using a photomask, the photomask including a substrate and a film coupled to substrate. The film is etched with a phase shifted assist feature, a low aspect ratio assist feature or phase shifted low aspect ... | 04/19/2005 |
| 6879020 | Semiconductor device Via-shaped copper interconnect lines (2) buried in an interlayer insulating film (8) are connected to gate interconnect lines (1) in the lowermost layer. A copper interconnect line (6) of a shield ring (5) is buried in the interlay... | 04/12/2005 |
| 6876062 | Seal ring and die corner stress relief pattern design to protect against moisture and metallic impurities An apparatus and method for protecting die corners in a semiconductor integrated circuit. At least one irregular seal ring having two sides can be configured, wherein the irregular seal ring is located at a corner of a die utilized in fabricating a semiconductor int... | 04/05/2005 |
| 6828220 | Flip chip-in-leadframe package and process A method for connecting a chip to a leadframe includes forming bumps on a die by a Au stud-bumping technique, and attaching the chip to the leadframe by thermo-compression of the bumps onto bonding fingers of the leadframe. Also a flip chip-in-leadframe package is m... | 12/07/2004 |
| 6825547 | Semiconductor device including edge bond pads A vertically mountable semiconductor device including at least one bond pad disposed on an edge thereof. The bond pad includes a conductive bump disposed thereon. The semiconductor device may also include a protective overcoat layer. The present invention also inclu... | 11/30/2004 |
| 6825501 | Robust Group III light emitting diode for high reliability in standard packaging applications A physically robust light emitting diode is disclosed that offers high-reliability in standard packaging and that will withstand high temperature and high humidity condition. The diode comprises a Group III nitride heterojunction diode with a p-type Group III nitrid... | 11/30/2004 |
| 6815805 | Method of fabricating an integrated circuit with a dielectric layer exposed to a hydrogen-bearing nitrogen source The present invention provides a flash memory integrated circuit and a method of fabricating the same. A tunnel dielectric in an erasable programmable read only memory (EPROM) device is nitrided with a hydrogen-bearing compound, particularly ammonia. Hydrogen is thu... | 11/09/2004 |
| 6803656 | Semiconductor device including combed bond pad opening A semiconductor device including bond pads disposed proximate an edge thereof, and an overcoat layer. The overcoat layer defines notches around each of the bond pads. The overcoat layer may be formed from a photoimageable material such as a photoimageable epoxy. The... | 10/12/2004 |
| 6797991 | Nitride semiconductor device The nitride semiconductor device includes: a substrate made of a III-V group compound semiconductor containing nitride; and a function region made of a III-V group compound semiconductor layer containing nitride formed on a main surface of the substrate. The main su... | 09/28/2004 |
| 6696705 | Power semiconductor component having a mesa edge termination A power semiconductor component having a mesa edge termination is described. The component has a semiconductor body with first and second surfaces. An inner zone of a first conductivity type is disposed in the semiconductor body. A first zone is disposed ... | 02/24/2004 |
| 6661080 | Structure for backside saw cavity protection A structure includes holes formed in a layer of tape. The holes are aligned over active areas on chips formed in a wafer. A custom vacuum chuck with a plurality of suction ports is aligned on the tape such that the suction ports contact only the tape and ... | 12/09/2003 |
| 6653663 | Nitride semiconductor device The nitride semiconductor device includes: a substrate made of a III-V group compound semiconductor containing nitride; and a function region made of a III-V group compound semiconductor layer containing nitride formed on a main surface of the substrate. ... | 11/25/2003 |
| 6635952 | Semiconductor device A semiconductor device comprises: a semiconductor substrate; an insulating layer provided on said semiconductor substrate; a first semiconductor layer provided on said insulating layer; a plurality of openings penetrating said first semiconductor layer an... | 10/21/2003 |
| 6621147 | In-process device with grooved coating layer on a semiconductor wafer for relieving surface tension A method used during the manufacture of a semiconductor device comprises providing a semiconductor wafer assembly, the assembly including a plurality of unsegmented semiconductor dice. A coating layer is formed over the semiconductor wafer assembly which ... | 09/16/2003 |
| 6611012 | Semiconductor device Described herein is a stacked package according to the present invention, wherein a plurality of tape carriers which seal semiconductor chips, are multilayered in upward and downward directions. In the stacked package, one ends of leads formed over the wh... | 08/26/2003 |
